In this paper, we present an area-efficient, globally asynchronous, locally synchronous
network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC …

CMOS microprocessors are limited in their capacity for clock speed improvement because of
increasing computing power, ie, they face a power-wall problem. Single-flux-quantum (SFQ) …

Chip multiprocessing has become an exciting new direction for system designers to deliver
increased performance by exploiting CMOS scaling. We discuss key design decisions facing …

This book provides design methods for Digital Signal Processors and Application Specific
Instruction set Processors, based on the author's extensive, industrial design experience …

As CMOS feature sizes continue to shrink and traditional microarchitectural methods for
delivering high performance (eg, deep pipelining) become too expensive and power …

A 34-million transistor stream processor system-on-chip (SoC) for signal, image, and video
processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5 …

This paper provides an overview of the Cell Broadband Engine™ Architecture (CBEA). The
CBEA defines a revolutionary extension to a more conventional processor organization and …

Microservices are emerging as a popular cloud-computing paradigm. Microservice
environments execute typically-short service requests that interact with one another via …

Matrix multiplication is one of the most common numerical operations, especially in the area
of dense linear algebra, where it forms the core of many important algorithms, including …

This work implements a computationally expensive chemical kinetics kernel from a large-
scale community atmospheric model on three multi-core platforms: NVIDIA GPUs using …