OverGen: Improving FPGA usability through domain-specific overlay generation
FPGAs have been proven to be powerful computational accelerators across many types of
workloads. The mainstream programming approach is high level synthesis (HLS), which …
workloads. The mainstream programming approach is high level synthesis (HLS), which …
SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip
As multicore processors find increasing adoption in domains such as aerospace and
medical devices where failures have the potential to be catastrophic, strong performance …
medical devices where failures have the potential to be catastrophic, strong performance …
Revisiting the high-performance reconfigurable computing for future datacenters
Modern datacenters are reinforcing the computational power and energy efficiency by
assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale …
assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale …
BRISC-V: An open-source architecture design space exploration toolbox
In this work, we introduce a platform for register-transfer level (RTL) architecture design
space exploration. The platform is an open-source, parameterized, synthesizable set of RTL …
space exploration. The platform is an open-source, parameterized, synthesizable set of RTL …
Heracles: a tool for fast RTL-based design space exploration of multicore processors
This paper presents Heracles, an open-source, functional, parameterized, synthesizable
multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile …
multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile …
Time-multiplexed FPGA overlay architectures: A survey
X Li, DL Maskell - ACM Transactions on Design Automation of Electronic …, 2019 - dl.acm.org
This article presents a comprehensive survey of time-multiplexed (TM) FPGA overlays from
the research literature. These overlays are categorized based on their implementation into …
the research literature. These overlays are categorized based on their implementation into …
Securing network-on-chips via novel anonymous routing
Network-on-Chip (NoC) is widely used as an efficient communication architecture in multi-
core and many-core System-on-Chips (SoCs). However, the shared communication …
core and many-core System-on-Chips (SoCs). However, the shared communication …
Networks on chip with provable security properties
In systems where a lack of safety or security guarantees can be catastrophic or even fatal,
noninterference is used to separate domains handling critical (or confidential) information …
noninterference is used to separate domains handling critical (or confidential) information …
A scalable many-core overlay architecture on an HBM2-enabled multi-die FPGA
The overlay architecture enables to raise the abstraction level of hardware design and
enhances hardware-accelerated applications' portability. In FPGAs, there is a growing …
enhances hardware-accelerated applications' portability. In FPGAs, there is a growing …
Securing network-on-chips against fault-injection and crypto-analysis attacks via stochastic anonymous routing
Network-on-chip (NoC) is widely used as an efficient communication architecture in multi-
core and many-core System-on-chips (SoCs). However, the shared communication …
core and many-core System-on-chips (SoCs). However, the shared communication …