ABC is a public-domain system for logic synthesis and formal verification of binary logic
circuits appearing in synchronous hardware designs. ABC combines scalable logic …

Last spring, in March 2010, Aaron Bradley published the first truly new bit-level symbolic
model checking algorithm since Ken McMillan's interpolation based model checking …

Conflict-driven clause learning (CDCL) satisfiability solvers can emit more than a
satisfiability result; they can also emit clausal proofs, resolution proofs, unsatisfiable cores …

Formal verification is a reliable and fully automatic technique for proving correctness of
hardware designs. Its main drawback is the high complexity of verification, and this problem …

The principle of strong induction, also known as k-induction is one of the first techniques for
unbounded SAT-based Model Checking (SMC). While elegant and simple to apply …

Satisfiability (SAT) solvers have become powerful tools to solve a wide range of
applications. In case SAT problems are satisfiable, it is easy to validate a witness. However …

Program analysis is on the brink of mainstream usage in embedded systems development.
Formal verification of behavioural requirements, finding runtime errors and test case …

In recent years, leading microprocessor companies have made huge investments to improve
the reliability of their products. Besides expanding their validation and CAD tools teams, they …

In earlier work on a limited form of extended resolution for CDCL based SAT solving, new
literals were introduced to factor out parts of learned clauses. The main goal was to shorten …

Incremental SAT solving under assumptions, introduced in Minisat, is in wide use. However,
Minisat's algorithm for incremental SAT solving under assumptions has two main drawbacks …