Three-dimensional semiconductor memory device including slit with lateral surfaces having periodicity

G Kawaguchi, M Fujita, H Inokuma… - US Patent …, 2018 - Google Patents
According to one embodiment, it includes a stacked body including N-number of layers (N is
an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating …

Semiconductor Device

BI Lee, JM Gu, T Lee, JH Cha - US Patent 10,515,974, 2019 - Google Patents
A semiconductor device includes a substrate having first and second regions, a gate
electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from …

Method of manufacturing semiconductor device

NJ Lee - US Patent 10,256,115, 2019 - Google Patents
(57) ABSTRACT A method of manufacturing a semiconductor device may include forming a
first stack structure by alternately stacking first material layers and second material layers …

Semiconductor device

YS Lee, TH Lee - US Patent 10,355,016, 2019 - Google Patents
A semiconductor device including: a substrate including a top surface configured to extend
in a first direction and a second direction that are perpendicular to each other; gate stack …

Non-volatile memory and fabricating method thereof

CL Chu, CH Chen, TC Chiu - US Patent 9,780,195, 2017 - Google Patents
A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a
second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of …

Semiconductor memory devices

G Zhang, H Kim, YH Kwon, P Sangwuk - US Patent 10,224,339, 2019 - Google Patents
Provided is a semiconductor memory device. The semicon ductor memory device includes a
peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and …

Vertical memory device including common source line structure

KS Kim - US Patent 10,535,599, 2020 - Google Patents
An integrated circuit (IC) device includes: a channel region that extends on the substrate to
penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the …

Semiconductor memory device

K Nakatsuka - US Patent 11,276,700, 2022 - Google Patents
(57) ABSTRACT A semiconductor memory device includes first conductive layers stacked on
a substrate; second conductive layers stacked on the substrate and apart from the first …

Memory cell structure of a three-dimensional memory device

DAI Xiaowang, Z Lu, J Chen, Q Tao, Y Hu… - US Patent …, 2024 - Google Patents
Various embodiments disclose a 3D memory device, including a substrate; a plurality of
conductor layers disposed on the substrate; a plurality of NAND strings disposed on the …

Vertical memory device with support layer

S Song, K Kim, S JoongShik, LIM Geunwon - US Patent 11,362,105, 2022 - Google Patents
A vertical memory device includes gate electrode structures, channels, first to third division
patterns, and a first support layer. The gate electrode structure includes gate electrodes …