Processing functions are offloaded to a memory controller for nonvolatile memory by a host
in connection with write data. The nonvolatile memory executes these functions, producing …

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane
NAND flash memory. In one embodiment, the host directly assigns physical addresses and …

This disclosure provides techniques for managing memory which match per-data metrics to
those of other data or to memory destination. In one embodiment, wear data is tracked for at …

This disclosure provides techniques hierarchical address virtualization within a memory
controller and configurable block device allocation. By performing address translation only …

Int. Cl. Described are memory modules that support different error GITC 7/10(2006.01)
detection and correction (EDC) schemes in both single-and GIC II/21093(2006.01) multiple …

Exemplary embodiments provide a tiered error correction code (ECC) Chipkill system,
comprising: a device ECC incorporated into at least a portion of a plurality of memory …

An example integrated circuit (IC) includes a network-on-chip (NoC), a master device
coupled to the NoC, a memory controller coupled to the NoC configured to control a memory …

This disclosure provides a memory controller for asymmetric non-volatile memory, such as
flash memory, and related host and memory system architectures. The memory controller is …

This disclosure provides for host-controller cooperation in managing NAND flash memory.
The controller maintains information for each erase unit which tracks memory usage. This …

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane
NAND flash memory. In one embodiment, the host directly assigns physical addresses and …