Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application

M Kammoun, A Ben Atitallah… - … Journal of Circuit …, 2017 - Wiley Online Library
The relationship between CPU and hardware accelerator is critical especially in some
systems that require intensive tasks and large amount of data to deal with such as video …

A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder

C Liu, W Shen, T Ma, Y Fan… - 2013 IEEE 10th …, 2013 - ieeexplore.ieee.org
The adoption of 35 prediction modes and quad-tree structure in intra coding of High
Efficiency Video Coding (HEVC) significantly improves the coding efficiency. In this paper, a …

An optimized hardware architecture for intra prediction for HEVC

M Kammoun, AB Atitallah… - … Applications and Systems …, 2014 - ieeexplore.ieee.org
In this paper, we propose an optimized hardware architecture for the implementation of intra
prediction in High Efficiency Video Coding standard (HEVC) decoder developed by the Joint …

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k× 2k H. 264/AVC video encoder

H Ren, Y Fan, X Chen, X Zeng - 17th Asia and South Pacific …, 2012 - ieeexplore.ieee.org
Intra prediction is the most important technology in H. 264/AVC intra frame encoder. But
there is extremely complicated data dependency and an immense amount of computation in …

A low complexity H. 264/AVC 4× 4 intra prediction architecture with macroblock/block reordering

M Orlandic, K Svarstad - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
The H. 264/AVC standard possesses high complexity features, among which intra prediction
characterized by high data dependency and immense amount of computation. Therefore the …

An efficient parallel execution for intra prediction in HEVC Video Encoder

DM Tung, TLT Dong, TT Anh - 2014 International Conference …, 2014 - ieeexplore.ieee.org
An efficient parallel execution of High-Efficiency Video Coding (HEVC) intra prediction is
proposed. The proposed parallel block based frame interleaving technique can remove the …

在PAC 平台利用軟體線程加速H. 264 視訊解碼

周哲賢, 蔡淳仁 - 2011 - ir.lib.nycu.edu.tw
本論文主旨在於多核心平台上使用software pipeline 方法對H. 264 解碼進行加速.
然而在多核心平台上使用software pipeline 會有許多overhead 容易導致效能降低, Stage …

Enhanced pipelined architecture of H. 264/AVC intra prediction

J Guo, Z Yang, J Zheng, D Guo - Signal Processing: Image Communication, 2016 - Elsevier
This paper presents a high-performance encoder for H. 264/AVC intra prediction. Due to
long data dependency loop of intra 4× 4 prediction and complex algorithms, improving …

GALS architecture of H. 264 video encoding system on DN-DualV6-PCIe-4 FPGA platform

Q Yang, T Wang, X Su, L Wang - 2012 IEEE 11th …, 2012 - ieeexplore.ieee.org
To manage the increasing complexity of modern digital systems, Globally-Asynchronous
Locally-Synchronous (GALS) is considered a promising solution, which is now widely …

An efficient architecture VLSI for 4× 4 intra prediction in HEVC standard

M Kammoun, AB Atitallah, H Loukil… - 10th International Multi …, 2013 - ieeexplore.ieee.org
The HEVC is a proposal of new video coding standard that will be used for a wide range of
applications like ULTRA-HD and 3D applications. MPEG and VCEG have established a …