Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
An mm-wave synthesizer with robust locking reference-sampling PLL and wide-range injection-locked VCO
In this article, a two-stage millimeter (mm)-wave frequency synthesizer with low in-band
noise and robust locking reference-sampling techniques is presented. Using a two-stage …
noise and robust locking reference-sampling techniques is presented. Using a two-stage …
A 28-nm FD-SOI 115-fs jitter PLL-based LO system for 24–30-GHz sliding-IF 5G transceivers
S Ek, T Påhlsson, C Elgaard, A Carlsson… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-
antenna transceivers is presented. The system is modular with one phase locked loop (PLL) …
antenna transceivers is presented. The system is modular with one phase locked loop (PLL) …
A harmonic-mixing PLL architecture for millimeter-wave application
A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by
the invariably large closed-loop gain and the high operation frequency of the voltage …
the invariably large closed-loop gain and the high operation frequency of the voltage …
A− 31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency …
To address the increasing demand for high-bandwidth mobile communications, 5G
technology is targeted to support data-rates up to 10Gb/s. To reach this goal, one of …
technology is targeted to support data-rates up to 10Gb/s. To reach this goal, one of …
An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators
This article presents a cascaded architecture of a frequency synthesizer to generate ultra-
low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The …
low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The …
[HTML][HTML] Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art
This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …
A 36.3-to-38.2GHz −216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter
D Weyer, MB Dayanik, S Jang… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Automotive radar and other mm-wave applications require high-quality frequency
synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the …
synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the …
A 50–66-GHz phase-domain digital frequency synthesizer with low phase noise and low fractional spurs
AI Hussein, S Vasadi… - IEEE Journal of Solid-State …, 2017 - ieeexplore.ieee.org
Digital phase-locked loop (DPLL) frequency synthesizers have become popular for wireless
applications in the sub-10-GHz range. However, mm-wave synthesizers still rely on analog …
applications in the sub-10-GHz range. However, mm-wave synthesizers still rely on analog …
An 82–107.6-GHz Integer- ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta–Sigma …
A W-band integer-N all-digital phase-locked loop (ADPLL) aiming for wide frequency tuning
range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally …
range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally …