Algorithms operating on a graph setting are known to be highly irregular and unstructured.
This leads to workload imbalance and data locality challenge when these algorithms are …

Applications' traffic tends to be bursty and the location of hot-spot nodes moves as time goes
by. This will significantly aggregate the blocking problem of wormhole-routed Network-on …

Addressing the challenges of extreme scale computing requires holistic design of new
programming models and systems that support those models. This paper discusses the …

Traditionally, hardware designs partitioned across multiple FPGAs have had low
performance due to the inefficiency of maintaining cycle-by-cycle timing among discrete …

We present DARSIM, a parallel, highly configurable, cycle-level network-on-chip simulator
based on an ingress-queued wormhole router architecture. The parallel simulation engine …

We present hornet, a parallel, highly configurable, cycle-level multicore simulator based on
an ingress-queued wormhole router network-on-chip (NoC) architecture. The parallel …

The personalized all-to-all collective exchange is one of the most challenging
communication patterns in HPC applications in terms of performance and scalability. In the …

We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based
on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine …

Recent years have seen the increased adoption of Coarse-Grained Reconfigurable
Architectures (CGRAs) as flexible, energy-efficient compute accelerators. Obtaining …

This paper presents Heracles, an open-source, functional, parameterized, synthesizable
multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile …