Logarithm-approximate floating-point multiplier
S Rezaei, R Omidi, A Azarpeyvand - Microelectronics Journal, 2022 - Elsevier
Approximate computing is a useful approach to save power and increase performance by
trading Energy and accuracy. This paper proposes an efficient inexact floating-point (FP) …
trading Energy and accuracy. This paper proposes an efficient inexact floating-point (FP) …
Enhanced FPGA linear phase FIR filter with amalgam multiplier
Designing high-performance integrated circuits that balance area, speed, and power is
increasingly challenging. This study optimises hardware implementation of FIR filters using …
increasingly challenging. This study optimises hardware implementation of FIR filters using …
Exploiting Area-Speed-Power Tradeoff of FPGA Designs on Multilayer Perceptron (MLP) Neural Network
AL Reed - 2020 - search.proquest.com
This dissertation presents four Field Programmable Gate Array (FPGA) design architectures
for handwritten digit recognition, in order to improve hardware efficiency in terms of …
for handwritten digit recognition, in order to improve hardware efficiency in terms of …