RACER: Bit-pipelined processing using resistive memory

MSQ Truong, E Chen, D Su, L Shen, A Glass… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
To combat the high energy costs of moving data between main memory and the CPU, recent
works have proposed to perform processing-using-memory (PUM), a type of processing-in …

3RSeT: Read disturbance rate reduction in STT-MRAM caches by selective tag comparison

E Cheshmikhani, H Farbeh… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Recent development in memory technologies has introduced Spin-Transfer Torque
Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip …

SALE: smartly allocating low-cost many-bit ECC for mitigating read and write errors in STT-RAM caches

MA Qureshi, J Park, S Kim - IEEE transactions on very large …, 2020 - ieeexplore.ieee.org
Spin-transfer torque RAM (STT-RAM) is a future technology for ON-chip caches. However, it
suffers from high read and write error rates. Concurrently dealing with these errors is quite …

Achieving DRAM-Like PCM by Trading Off Capacity for Latency

I Alam, P Gupta - IEEE Transactions on Computers, 2024 - ieeexplore.ieee.org
Phase Change Memory (PCM) is considered one of the most promising scalable non-
volatile main memory alternatives to DRAM. It provides 4x-5x cost per bit advantage over …

[图书][B] Lightweight Opportunistic Memory Resilience

I Alam - 2021 - search.proquest.com
The reliability of memory subsystems is worsening rapidly and needs to be considered as
one of the primary design objectives when designing today's computer systems. From on …

Enabling Recovery of Secure Non-Volatile Memories

M Ye - 2020 - stars.library.ucf.edu
Emerging non-volatile memories (NVMs), such as phase change memory (PCM), spin-
transfer torque RAM (STT-RAM) and resistive RAM (ReRAM), have dual memory-storage …