A novel power loop parasitic extraction approach for paralleled discrete SiC MOSFETs on multilayer PCB
J Chen, H Peng, Z Cheng, X Liu, Q Xin… - IEEE Journal of …, 2021 - ieeexplore.ieee.org
Paralleled discrete SiC MOSFETs lead to high current capability at low costs. Current
sharing is a critical issue for paralleling design with significant impacts on switching losses …
sharing is a critical issue for paralleling design with significant impacts on switching losses …
A Screening Method for Improving Transient Current Sharing of Paralleled SiC MOSFETs Based on Spectral Clustering
J Yang, Y Gan, H Cui, Y Nie, W Fan… - 2024 IEEE Applied …, 2024 - ieeexplore.ieee.org
SiC MOSFETs are often used in parallel in power modules to increase current capacity, but
due to mismatches of circuit parasitic inductance and chip parameters, there is a serious …
due to mismatches of circuit parasitic inductance and chip parameters, there is a serious …
Excellent Static and Dynamic Scaling of Power Handling Capability of the BaSIC (DMM) Topology with 1.2 kV SiC Power MOSFETs
Enhanced short-circuit (SC) withstand capability for SiC Power MOSFETs has been recently
achieved using the BaSIC (DMM) topology which employs a Gate-Source-Shorted Si …
achieved using the BaSIC (DMM) topology which employs a Gate-Source-Shorted Si …