This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-
recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) and QRHIL-LC (low …

With the rapid advancement of CMOS technologies, nano-scale CMOS latches have
become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations …

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs.
First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch …

In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets
(MNUs) induced in harsh radiation environments. The existing verification of the reliability of …

Static Random Access Memory (SRAM) is primarily used as a memory storage element,
which is susceptible to radiation-induced Single Event Upsets (SEUs). Hence, a robust …

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event
Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge …

This paper presents two novel memory cell designs that can completely tolerate double-
node upsets. First, a layout dependent cell is proposed. Since the cell has many redundant …

To meet the requirements of both high reliability and low power in low-orbit aerospace
applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable …

Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This
paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node …

As CMOS technology scaling pushes towards the reduction of the length of transistors,
electronic circuits face numerous reliability issues, and in particular nodes of D-latches at …