A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

A Sachdeva, D Kumar, E Abbasian - AEU-International Journal of …, 2023 - Elsevier
Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to
conventional CMOS transistors due to superior transport properties, improved current …

Scaling beyond 7nm node: An overview of gate-all-around fets

W Hu, F Li - 2021 9th international symposium on next …, 2021 - ieeexplore.ieee.org
Gate-all-around (GAA) is a promising MOSFET structure to continue scaling down the size of
CMOS devices beyond 7 nm technology node. This paper gives an overview of different …

Performance and device design based on geometry and process considerations for 14/16-nm strained FinFETs

FAM Rezali, NAF Othman, M Mazhar… - … on Electron Devices, 2016 - ieeexplore.ieee.org
The multigated architecture of FinFETs appear attractive for continued CMOS scaling with
the addition of discrete fin sizing that brings a new variable into the design. In this paper, a …

Spacer engineering for performance enhancement of junctionless accumulation‐mode bulk FinFETs

K Biswas, A Sarkar, CK Sarkar - IET Circuits, Devices & …, 2017 - Wiley Online Library
This study investigates the performance of the junctionless accumulation‐mode (JAM) bulk
FinFETs. Different electrical parameters are simulated and analysed for the device with …

Impact of Gate Length and Doping Variation on the DC and Analog/RF Performance of sub - 3nm Stacked Si Gate-All-Around Nanosheet FET

N Yadav, S Jadav, G Saini - Silicon, 2023 - Springer
Abstract The nanosheet Field Effect Transistors (FETs) are the promising device architecture
for sub-5 nm technology node as per the International Roadmap for Devices and Systems …

Geometrical variability impact on the performance of sub-3 nm gate-all-around stacked nanosheet FET

N Yadav, S Jadav, G Saini - Silicon, 2022 - Springer
To meet the scaling targets and continue with Moore's Law, the transition from FinFET to
Gate-All-Around (GAA) nanosheet Field Effect Transistors (FETs) is the necessity for low …

The effect of shallow trench isolation and sinker on the performance of dual-gate LDMOS device

S Chahar, GM Rather - IEEE Transactions on Electron …, 2018 - ieeexplore.ieee.org
In this paper, a dual-gate laterally double-diffused metal-oxide-semiconductor (DG-LDMOS)
device with shallow trench isolation (STI) and sinker at the source side has been proposed …

Temperature-dependent short-channel parameters of FinFETs

RR Das, S Maity, A Choudhury, A Chakraborty… - Journal of …, 2018 - Springer
The remarkable development and continual proliferation of research in the nanotechnology
field have led to improvement in the efficiency of elementary devices. To improve their …

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

S Panchanan, R Maity, A Baidya… - Engineering Research …, 2023 - iopscience.iop.org
Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect -
IOPscience Skip to content IOP Science home Accessibility Help Search Journals Journals list …

A study on modeling and simulation of Multiple-Gate MOSFETs

M Singh, G Kumar, S Bordoloi… - Journal of Physics …, 2016 - iopscience.iop.org
Endless scaling of planar MOSFET over the past four decades has delivered proliferating
transistor density and performance to integrated circuits (ICs) at the cost of increase in short …