This paper discusses the design of on-chip transformer-based fourth order filters, suitable for
mm-Wave highly sensitive broadband low-noise amplifiers (LNAs) and receivers (RXs) …

A wideband amplitude to phase (AM-PM) compensated class-AB power amplifier (PA)
suitable for highly integrated fifth-generation phased arrays is designed in 0.9-V 28-nm …

We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet
of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital …

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …

This brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for
fifth generation (5G) applications realized in 28-nm LP CMOS. Based on the unique set of …

In this paper, we present an all-digital ring oscillator (RO)-based Bluetooth low-energy (BLE)
transmitter (TX) for ultra-low-power radios in short range Internet-of-Things (IoT) …

We propose a new transmitter architecture for ultra-low power radios in which the most
energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS …

A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …

This paper investigates design considerations and challenges of integrating on-chip
antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a …

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL)
powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs …