Next-generation internet of things (iot): Opportunities, challenges, and solutions
It is predicted that by 2025, all devices will be connected to the Internet, subsequently
causing the number of devices connected with the Internet to rise. As indicated by Cisco …
causing the number of devices connected with the Internet to rise. As indicated by Cisco …
Application mapping using cuckoo search optimization with Lévy flight for NoC-based system
MJ Mohiz, NK Baloch, F Hussain, S Saleem… - IEEE …, 2021 - ieeexplore.ieee.org
Network on chip (NoC) is a promising communication infrastructure for multiple cores on a
chip to exchange data efficiently. In such NoC architecture, application mapping is a process …
chip to exchange data efficiently. In such NoC architecture, application mapping is a process …
Network-on-Chip (NoC) Applications for IoT-Enabled Chip Systems: Latest Designs and Modern Applications
B Guo, H Liu, L Niu - … Journal of High Speed Electronics and …, 2024 - World Scientific
Network-on-Chip (NoC) technology has emerged as a critical innovation in the field of
integrated circuit design, addressing the growing demands for efficient, scalable, and high …
integrated circuit design, addressing the growing demands for efficient, scalable, and high …
An efficient and cost effective application mapping for network-on-chip using Andean condor algorithm
Advancement in very large scale integration (VLSI) technologies and the ever-shrinking size
of the transistors have led the semiconductor designers to create a multiprocessor system on …
of the transistors have led the semiconductor designers to create a multiprocessor system on …
An optimized nature-inspired metaheuristic algorithm for application mapping in 2D-NoC
Mapping application task graphs on intellectual property (IP) cores into network-on-chip
(NoC) is a non-deterministic polynomial-time hard problem. The evolution of network …
(NoC) is a non-deterministic polynomial-time hard problem. The evolution of network …
SB-Router: A swapped buffer activated low latency network-on-chip router
Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its
performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally …
performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally …
Dynamic Fault Tolerance Approach for Network-on-Chip Architecture
K Khalil, A Kumar, M Bayoumi - IEEE Journal on Emerging and …, 2024 - ieeexplore.ieee.org
Network-on-Chip (NoC) architecture provides speed-efficient and scalable communication
in complex integrated circuits. Attaining fault tolerance in NoC architectures is an ongoing …
in complex integrated circuits. Attaining fault tolerance in NoC architectures is an ongoing …
Packet Simulator Tool for Many-Core Systems
PCD Paris, EC Pedrino - 2023 IEEE International Conference …, 2023 - ieeexplore.ieee.org
With recent advances in technology, many-core systems have become increasingly common
in high-performance computing applications, such as embedded systems and artificial …
in high-performance computing applications, such as embedded systems and artificial …
Asynchronous Circular Buffers based on FIFO for Network on Chips
M Menaka, K Aishwarya… - … Conference on Circuit …, 2023 - ieeexplore.ieee.org
In multicore System-on-Chips (SoCs), Network on Chip (NoC) is utilized to facilitate on chip
communication due to its benefits over bus-based topologies, specifically as chip sizes go …
communication due to its benefits over bus-based topologies, specifically as chip sizes go …
Methods for Constructing High-Performance Interconnects in System-on-Chip Designs
KD Lyubavin, DV Telpukhov - 2024 IEEE International Multi …, 2024 - ieeexplore.ieee.org
This paper explores the development of high-performance interconnects essential for
System-on-Chip (SoC) designs, focusing on high bandwidth, low latency, and configuration …
System-on-Chip (SoC) designs, focusing on high bandwidth, low latency, and configuration …