Stacked die assembly
EC Wu, R Chaware - US Patent 8,704,384, 2014 - Google Patents
(57) ABSTRACT A stacked die assembly for an IC includes a? rst interposer; a second
interposer; a? rst integrated circuit die, a second inte grated circuit die, and a plurality of …
interposer; a? rst integrated circuit die, a second inte grated circuit die, and a plurality of …
Reducing stress in multi-die integrated circuit structures
B Banijamali - US Patent 8,704,364, 2014 - Google Patents
An integrated circuit structure can include a first interposer and a second interposer. The first
interposer and the second interposer can be coplanar. The integrated circuit structure further …
interposer and the second interposer can be coplanar. The integrated circuit structure further …
Flexible sized die for use in multi-die integrated circuit
RC Camarota - US Patent 9,026,872, 2015 - Google Patents
An integrated circuit (IC) structure can include a first die and a second die. The second die
can include a first base unit and a second base unit. Each of the first base unit and the …
can include a first base unit and a second base unit. Each of the first base unit and the …
SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
L Lin, T Yeh - US Patent App. 14/495,575, 2016 - freepatentsonline.com
A semiconductor package structure includes a semiconductor substrate including a plurality
of through substrate vias (TSV) extending from a first surface to a second surface of the …
of through substrate vias (TSV) extending from a first surface to a second surface of the …
Coaxial through via with novel high isolation cross coupling method for 3D integrated circuits
FW Kuo, WS Liao, CP Jou, C Huan-Neng… - US Patent …, 2021 - Google Patents
(57) ABSTRACT A semiconductor package includes a first semiconductor device, a second
semiconductor device vertically positioned above the first semiconductor device, and a …
semiconductor device vertically positioned above the first semiconductor device, and a …
Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging
FW Kuo, WS Liao - US Patent 10,037,897, 2018 - Google Patents
(57) ABSTRACT A semiconductor package includes a first semiconductor element, an
insulating layer, and a second semiconductor element. The first semiconductor element …
insulating layer, and a second semiconductor element. The first semiconductor element …
Package substrate with embedded noise shielding walls
D Hu - US Patent 10,290,586, 2019 - Google Patents
A package substrate with embedded noise shielding walls is disclosed. One of the
embodiment comprises a signal line S sandwiched by a left shielding wall W1 and a right …
embodiment comprises a signal line S sandwiched by a left shielding wall W1 and a right …
Semiconductor device components and methods
BL Lin, JH Lin, MH Hsieh, LD Chen, JR Shih… - US Patent …, 2014 - Google Patents
Semiconductor device components and methods are disclosed. In one embodiment, a
semiconductor device component includes a conductive segment having a first surface, a …
semiconductor device component includes a conductive segment having a first surface, a …
Oversized interposer
T Hisamura - US Patent 8,957,512, 2015 - Google Patents
6,429,509 6,448,808 6,500,696 6,512,573 6,525.407 6,559,531 6,583,854 6,611,635
6,731,009 6,734,553 6,870,271 6,930,378 6,944,809 6,972.487 6,984,889 6,992.395 …
6,731,009 6,734,553 6,870,271 6,930,378 6,944,809 6,972.487 6,984,889 6,992.395 …
Monolithic integrated circuit die having modular die regions stitched together
RC Camarota - US Patent 9,547,034, 2017 - Google Patents
An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the
monolithic integrated circuit die has a plurality of modular die regions. The modular die …
monolithic integrated circuit die has a plurality of modular die regions. The modular die …