Speed, power and area efficient 2D FIR digital filter using vedic multiplier with predictor and reusable logic
VD Christilda, A Milton - Analog Integrated Circuits and Signal Processing, 2021 - Springer
The main goal of this paper is to design an efficient 2D FIR digital filter for digital image
processing and digital signal processing applications. To optimize filter speed, area and …
processing and digital signal processing applications. To optimize filter speed, area and …
Research on the recognition of machining conditions based on sound and vibration signals of a CNC milling machine
WL Chu, MJ Xie, QW Chang, HT Yau - IEEE Sensors Journal, 2022 - ieeexplore.ieee.org
Machining conditions of real-time identification tools is a key and trending issue for the
industry. This paper focuses on identifying whether machining is performed as well as the …
industry. This paper focuses on identifying whether machining is performed as well as the …
[HTML][HTML] Power and area efficient FIR filter architecture in digital encephalography systems
S Janwadkar, R Dhavse - e-Prime-Advances in Electrical Engineering …, 2023 - Elsevier
In the process of Electroencephalogram (EEG) acquisition, the electrical signals from the
brain are contaminated by numerous noise sources and artifacts. American Clinical …
brain are contaminated by numerous noise sources and artifacts. American Clinical …
Comparative study of FFA architectures using different multiplier and adder topologies
Parallel FIR filter is the prime block of many modern communication application such as
MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques …
MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques …
Implementation of FIR filter using reversible modified carry select adder
R Arun Sekar, S Sasipriya - Concurrency and Computation …, 2019 - Wiley Online Library
Any arithmetic operation can be performed using the method of Reversible process which
allows minimum arithmetic execution. An essential scenario for achieving this condition is …
allows minimum arithmetic execution. An essential scenario for achieving this condition is …
Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
This paper proposes an efficient high‐order finite impulse response (FIR) filter structure for
field programmable gate array (FPGA)‐based applications with simultaneous digital signal …
field programmable gate array (FPGA)‐based applications with simultaneous digital signal …
Design of FFT processor using low power Vedic multiplier for wireless communication
Abstract Digital Signal Processing (DSP) is a very significant and active research area. High
throughput is a requirement for most wireless communication systems. The critical …
throughput is a requirement for most wireless communication systems. The critical …
An efficient fir filter based on hardware sharing architecture using csd coefficient grouping for wireless application
AK Srivastava, K Raj - Wireless Personal Communications, 2022 - Springer
FIR filter is an essential part of digital signal processing that is extensively used in many
areas such as wireless applications and digital processing system. The FIR filter design is …
areas such as wireless applications and digital processing system. The FIR filter design is …
Low power single precision BCD floating–point Vedic multiplier
V Ramya, R Seshasayanan - Microprocessors and Microsystems, 2020 - Elsevier
In this paper, the Binary coded decimal floating-point multiplier (BCD-FPM) and Binary
floating-point multiplier (BFPM) with binary to BCD (B2BCD) converter are proposed using …
floating-point multiplier (BFPM) with binary to BCD (B2BCD) converter are proposed using …
Design and evaluation of a FIR filter using hybrid adders and Vedic multipliers
In this paper, FIR filter of 45nm technological node has been presented, which is a basic
filter in DSP applications. Hybrid Adder has been introduced to improve cost and power …
filter in DSP applications. Hybrid Adder has been introduced to improve cost and power …