Methods for linear systems of circuit delay differential equations of neutral type

A Bellen, N Guglielmi, AE Ruehli - IEEE Transactions on …, 1999 - ieeexplore.ieee.org
Delay differential equations (DDEs) occur in many different fields including circuit theory.
Circuits which include delayed elements have become more important due to the increase …

Nonorthogonal PEEC formulation for time-and frequency-domain EM and circuit modeling

AE Ruehli, G Antonini, J Esch, J Ekman… - IEEE Transactions …, 2003 - ieeexplore.ieee.org
Electromagnetic solvers based on the partial element equivalent circuit (PEEC) approach
have proven to be well suited for the solution of combined circuit and EM problems. The …

Progress in the methodologies for the electrical modeling of interconnects and electronic packages

AE Ruehli, AC Cangellaris - Proceedings of the IEEE, 2001 - ieeexplore.ieee.org
The rapid growth of the electrical modeling and analysis of the interconnect structure, both at
the electronic chip and package level, can be attributed to the increasing importance of the …

Fast integral equation solvers in computational electromagnetics of complex structures☆

WC Chew, HY Chao, TJ Cui, CC Lu, S Ohnuki… - … Analysis with Boundary …, 2003 - Elsevier
This paper reviews the recent progress of fast integral equation solvers at the Center for
Computational Electromagnetics and Electromagnetics laboratory, University of Illinois at …

The Partial Elements Equivalent Circuit Method: The State of the Art

G Antonini, AE Ruehli, D Romano… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This year marks about half a century since the birth of the technique known as the partial
element equivalent circuit modeling approach. This method was initially conceived to model …

Circuit and method for suppression of electromagnetic coupling and switching noise in multilayer printed circuit boards

WE McKinzie III, SD Rogers - US Patent 7,215,007, 2007 - Google Patents
Apparatus for Suppressing noise and electromagnetic cou pling in the printed circuit board
of an electronic device includes an upper conductive plate and an array of conduc tive …

Full-wave PEEC time-domain method for the modeling of on-chip interconnects

PJ Restle, AE Ruehli, SG Walker… - IEEE Transactions on …, 2001 - ieeexplore.ieee.org
With the advances in the speed of high-performance chips, inductance effects in some on-
chip interconnects have become significant. Specific networks such as clock distributions …

Analysis of 3-D interconnect structures with PEEC using SPICE

C Wollenberg, A Gurisch - IEEE Transactions on …, 1999 - ieeexplore.ieee.org
This paper discusses the possibilities of using the circuit simulation program, simulation
program with integrated circuit emphasis (SPICE) for the simulation of partial element …

A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation

J Cullum, A Ruehli, T Zhang - IEEE Transactions on Circuits …, 2000 - ieeexplore.ieee.org
The continuous improvement in the performance and the increases in the sizes of VLSI
systems make electrical interconnect and package (EIP) design and modeling increasingly …

Electromagnetic model order reduction for system-level modeling

AC Cangellaris, M Celik, S Pasha… - IEEE Transactions on …, 1999 - ieeexplore.ieee.org
Reduced-order modeling of an electromagnetic system is understood as the approximation
of a continuous or discrete model of the system by one of substantially lower order, yet …