This paper deals with the process of Transformation and Quantization that is carried out on
each inter-predicted residual block in a video encoding process and their reduced …

In this paper, high throughput area-efficient system-on-chip-based (SoC) forward/inverse
integer transform (FIT/IIT) modules for H. 264/AVC are proposed. High throughput can be …

In this paper, an application-specific instruction set processor (ASIP)-controlled inverse
integer transform IP block on a system-on-chip (SoC) platform is proposed. The proposed …

This paper proposes a novel implementation of the core processors, the integer transform
and quantization for H. 264 video encoder using an FPGA. It is capable of processing the …

By imposing a single hierarchy on data, XML makes queries brittle in the sense that a query
might fail to produce the desired result if it is executed on the same data organized in a …

In this paper, low latency and high throughput texture coding architectures are proposed to
realize the 4× 4 integer/Hadamard transforms, the quantization (Q), and the inverse …

In this paper, we propose novel hardware architecture for intra 16× 16 module for the
macroblock engine of a new video coding standard H. 264. To reduce the cycle of intra …

提出了在FPGA 上实现H. 264 中整数变换量化的方法, 设计了基于动态数据宽度和流水线技术的
软核(IP), 在处理速度和硬件资源方面分别进行优化, 此软核作为PowerPC …

In this paper, a high normalized aggregate throughput system-on-chip-based inverse integer
transform (IIT) module for H. 264/AVC is proposed. Aggregate throughput involves …

RECENT advances in computing and communication technology have ex-panded the
boundaries of communication systems to include a rich visual dimension. Standards-based …