Techniques are disclosed for transistor fabrication including a sacrificial protective layer for
source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer …

Devices and methods are provided for fabricating shared contact trenches for source/drain
layers of n-type and p-type field-effect transistor devices, wherein the shared contact …

(57) ABSTRACT A semiconductor device includes a first fin-type pattern and a second fin-
type pattern which protrude upwardly from an upper surface of a field insulating film and …

This disclosure relates to a method of replacement metal gate patterning for nanosheet
devices including: forming a first and a second nanosheet stack on a substrate, the first and …

US9985026B2 - Transistor, integrated circuit and method of fabricating the same - Google
Patents US9985026B2 - Transistor, integrated circuit and method of fabricating the same …

BACKGROUND Different semiconductor structures may be fabricated to have one or more
different device characteristics. Such as Switching speed, leakage power consumption, etc …

US10236350B2 - Method, apparatus and system for a high density middle of line flow - Google
Patents US10236350B2 - Method, apparatus and system for a high density middle of line flow …

The present invention provides improved tech niques for implementing a dual silicide in an
electronic device process flow. In one aspect of the invention, a method for silicidation is …

Provided is a semiconductor device including a substrate with an active pattern, a gate
electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The …

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Session 8,143,655 B2 3/2012 Chiola 8,148,749 B2 4/2012 Grebs et al. 8, 168,466 B2 …