A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration
M El-Chammas, B Murmann - IEEE journal of solid-state …, 2011 - ieeexplore.ieee.org
This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To
improve the dynamic performance at high input frequencies, a statistics-based background …
improve the dynamic performance at high input frequencies, a statistics-based background …
A/D converter trends: Power dissipation, scaling and digitally assisted architectures
B Murmann - 2008 IEEE Custom Integrated Circuits …, 2008 - ieeexplore.ieee.org
This paper summarizes recent trends in the area of low-power A/D conversion. Survey data
collected over the past eleven years indicates that the power efficiency of ADCs has …
collected over the past eleven years indicates that the power efficiency of ADCs has …
Analog circuit design in nanoscale CMOS technologies
LL Lewyn, T Ytterdal, C Wulff… - Proceedings of the …, 2009 - ieeexplore.ieee.org
As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into
the nanometer range, a number of major nonidealities must be addressed and overcome to …
the nanometer range, a number of major nonidealities must be addressed and overcome to …
A CMOS 6-bit 16-GS/s time-interleaved ADC using digital background calibration techniques
CC Huang, CY Wang, JT Wu - IEEE Journal of Solid-State …, 2011 - ieeexplore.ieee.org
An 8-channel 6-bit 16-GS/s time-interleaved analog-to-digital converter (TI ADC) was
fabricated using a 65 nm CMOS technology. Each analog-to-digital channel is a 6-bit flash …
fabricated using a 65 nm CMOS technology. Each analog-to-digital channel is a 6-bit flash …
A 480 mW 2.6 GS/s 10b time-interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm CMOS
This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register
(SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop …
(SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop …
A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm digital CMOS
A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice
consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic …
consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic …
RF analog beamforming fan filters using CMOS all-pass time delay approximations
C Wijenayake, Y Xu, A Madanayake… - … on Circuits and …, 2012 - ieeexplore.ieee.org
A continuous-time (CT) radio frequency (RF) antenna array beamformer and analog circuit
based on a discrete-space-continuous-time (DSCT) 2-D fan-filter having transfer function …
based on a discrete-space-continuous-time (DSCT) 2-D fan-filter having transfer function …
16.3 A single-channel 5.5 mW 3.3 GS/s 6b fully dynamic pipelined ADC with post-amplification residue generation
Multi-GS/s ADCs are key blocks for ADC-based serial links and mm-wave 5G receivers. The
fastest architecture is the flash ADC [1], but the exponentially growing complexity with …
fastest architecture is the flash ADC [1], but the exponentially growing complexity with …
A 500 mW ADC-based CMOS AFE with digital calibration for 10 Gb/s serial links over KR-backplane and multimode fiber
J Cao, B Zhang, U Singh, D Cui… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based
transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) …
transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) …
A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
An asynchronous 8× interleaved redundant SAR ADC achieving 8.8 GS/s at 35mW and 1V
supply is presented. The ADC features pass-gate selection clocking scheme for time-skew …
supply is presented. The ADC features pass-gate selection clocking scheme for time-skew …