(57) ABSTRACT A method is provided that includes: determining a minimum clock cycle that
can be used to propagate a signal about the critical cycle in a circuit design; wherein the …

A method is provided that includes: determining a minimum clock cycle that can be used to
propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a …

Traditional timing-driven placement considers only combinational delays and does not take
into account the potential of subsequent sequential optimization steps. As a result, the …

A method is provided that includes: determining a minimum clock cycle that can be used to
propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a …

This paper describes a delay insertion method that improves the efficiency of clock skew
scheduling. Clock skew scheduling is performed on synchronous circuits in order to improve …

Clock skew scheduling is a technique that intentionally introduces skews to memory
elements to improve the performance of a sequential circuit. It was shown in (Ravindran …

Given several specific clocking domains, the peak current minimization problem can be
formulated as a 0-1 integer linear program. However, if the number of binary variables is …

Proposed post-clock-tree-synthesis (CTS) optimization method is delay buffering at the
leaves of the clock tree to implement a limited version of clock skew scheduling. The method …

Peak power reduction has been a critical challenge in the design of integrated circuits
impacting the chip's performance and reliability. The reduction of peak power also reduces …

In this paper, we propose a skew-programmable clock-routing architecture. The skews can
be adjusted using programmable delay elements (PDEs) which we insert into the clock …