A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-
speed applications. The CD characteristic of this logic style regardless of the logic type …

In VLSI system. The integrated circuit design has important role. The various parameters are
considering for design the circuit. The important parameters are power and delay. The …

A large number of web databases are only accessible through proprietary form-like
interfaces which require users to query the system by entering desired values for a few …

An adiabatic constant delay (ACD) logic style is proposed in this paper, for full-custom high-
speed and low power applications. The characteristic of ACD logic style will not depend …

In this paper a new design technique is proposed using FTL (Feed through Logic) concept
for high performance dynamic CMOS logic with high noise immunity and low power. FTL …

This paper proposes Field Programmable Gate Array (FPGA) based architecture for simple,
portable, low cost anemia detector by implementing in verilog HDL. Noninvasive diagnosis …

To improve noise tolerance of the dynamic logic circuits with leakage current reduction, a
new noise tolerant technique is proposed here. Average noise threshold energy (ANTE) …

A new framework is proposed for the evaluation and comparison of high‐speed parallel‐
prefix adders. The framework specifies input registers and latches and requires sum …

This paper presents the new design of CD logic based style named as Bride Logic style.
Low power consumption with high performance of the circuit is one of the important factors …

This paper presents the review work on Constant Delay (CD) Logic. Dynamic
(Complementary Metal Oxide Semiconductor) CMOS circuit style is introduced which allows …