Methods for evaluating and covering the design space during early design development

M Gries - Integration, 2004 - Elsevier
This paper gives an overview of methods used for design space exploration (DSE) of micro-
architectures and systems. The DSE problem generally considers two orthogonal issues:(I) …

A first-order superscalar processor model

TS Karkhanis, JE Smith - ACM SIGARCH Computer Architecture News, 2004 - dl.acm.org
A proposed performance model for superscalar processorsconsists of 1) a component that
models the relationshipbetween instructions issued per cycle and the sizeof the instruction …

SynFull: Synthetic traffic models capturing cache coherent behaviour

M Badr, NE Jerger - ACM SIGARCH Computer Architecture News, 2014 - dl.acm.org
Modern and future many-core systems represent complex architectures. The communication
fabrics of these large systems heavily influence their performance and power consumption …

Modeling superscalar processors via statistical simulation

S Nussbaum, JE Smith - Proceedings 2001 International …, 2001 - ieeexplore.ieee.org
Statistical simulation is a technique for fast performance evaluation of superscalar
processors. First, intrinsic statistical information is collected from a single detailed simulation …

Using the caremap with health incidents statistics for generating the realistic synthetic electronic healthcare record

S McLachlan, K Dube… - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
The de-personalised Electronic Healthcare Record (EHR) for secondary use has suffered re-
identification. The Realistic Synthetic EHR (RS-EHR) is a promising solution safe from the …

Fast, accurate, and scalable memory modeling of GPGPUs using reuse profiles

Y Arafa, AH Badawy, G Chennupati, A Barai… - Proceedings of the 34th …, 2020 - dl.acm.org
In this paper, we introduce an accurate and scalable memory modeling framework for
General Purpose Graphics Processor units (GPGPUs), PPT-GPU-Mem. That is Performance …

Proxy benchmarks for emerging big-data workloads

R Panda, LK John - 2017 26th International Conference on …, 2017 - ieeexplore.ieee.org
Early design-space evaluation of computer-systems is usually performed using performance
models such as detailed simulators, RTL-based models etc. Unfortunately, it is very …

West: Cloning data cache behavior using stochastic traces

G Balakrishnan, Y Solihin - IEEE International Symposium on …, 2012 - ieeexplore.ieee.org
Cache designers need an in-depth understanding of end user workloads, but certain end
users are apprehensive about sharing code or traces due to the proprietary or confidential …

EXPERT: expedited simulation exploiting program behavior repetition

W Liu, MC Huang - Proceedings of the 18th annual international …, 2004 - dl.acm.org
Studying program behavior is a central component in architectural designs. In this paper, we
study and exploit one aspect of program behavior, the behavior repetition, to expedite …

Fast and accurate exploration of multi-level caches using hierarchical reuse distance

RKV Maeda, Q Cai, J Xu, Z Wang… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
Exploring the design space of the memory hierarchy requires the use of effective
methodologies, tools, and models to evaluate different parameter values. Reuse distance is …