A comprehensive exploration of languages for parallel computing
Software-intensive systems in most domains, from autonomous vehicles to health, are
becoming predominantly parallel to efficiently manage large amount of data in short (even …
becoming predominantly parallel to efficiently manage large amount of data in short (even …
FlexGrip: A soft GPGPU for FPGAs
K Andryc, M Merchant, R Tessier - … International Conference on …, 2013 - ieeexplore.ieee.org
Over the past decade, soft microprocessors and vector processors have been extensively
used in FPGAs for a wide variety of applications. However, it is difficult to straightforwardly …
used in FPGAs for a wide variety of applications. However, it is difficult to straightforwardly …
Synthesis of platform architectures from OpenCL programs
The problem of automatically generating hardware modules from a high level representation
of an application has been at the research forefront in the last few years. In this paper, we …
of an application has been at the research forefront in the last few years. In this paper, we …
High‐Level Synthesis: Productivity, Performance, and Software Constraints
FPGAs are an attractive platform for applications with high computation demand and low
energy consumption requirements. However, design effort for FPGA implementations …
energy consumption requirements. However, design effort for FPGA implementations …
Cupbop: Making cuda a portable language
CUDA is designed specifically for NVIDIA GPUs and is not compatible with non-NVIDIA
devices. Enabling CUDA execution on alternative backends could greatly benefit the …
devices. Enabling CUDA execution on alternative backends could greatly benefit the …
High level synthesis of stereo matching: Productivity, performance, and software constraints
FPGAs are an attractive platform for applications with high computation demand and low
energy consumption requirements. However, design effort for FPGA implementations …
energy consumption requirements. However, design effort for FPGA implementations …
Enabling development of OpenCL applications on FPGA platforms
K Shagrithaya, K Kępa… - 2013 IEEE 24th …, 2013 - ieeexplore.ieee.org
High-level FPGA synthesis tools aim to increase the productivity of FPGAs and to adopt them
among software developers and domain experts. OpenCL is a specification introduced for …
among software developers and domain experts. OpenCL is a specification introduced for …
SOFF: An OpenCL high-level synthesis framework for FPGAs
Recently, OpenCL has been emerging as a programming model for energy-efficient FPGA
accelerators. However, the state-of-the-art OpenCL frameworks for FPGAs suffer from poor …
accelerators. However, the state-of-the-art OpenCL frameworks for FPGAs suffer from poor …
High-level synthesis with behavioral-level multicycle path analysis
H Zheng, ST Gurumani, L Yang… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
High-level synthesis (HLS) tools generate register-transfer level (RTL) hardware
descriptions from behavioral-level specifications through resource allocation, scheduling …
descriptions from behavioral-level specifications through resource allocation, scheduling …
FCUDA-NoC: A scalable and efficient network-on-chip implementation for the CUDA-to-FPGA flow
High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified
Device Architecture (CUDA), enables efficient description and implementation of …
Device Architecture (CUDA), enables efficient description and implementation of …