Sub-sampling PLL techniques
In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N 2,
when referred to the VCO output, due to the divide-by-N in the feedback path. It often …
when referred to the VCO output, due to the divide-by-N in the feedback path. It often …
A 2.5–5.75-GHz ring-based injection-locked clock multiplier with background-calibrated reference frequency doubler
A Elkholy, D Coombs, RK Nandwana… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is
presented. It employs a background-calibrated reference frequency doubler to increase the …
presented. It employs a background-calibrated reference frequency doubler to increase the …
On advance towards sub-sampling technique in phase locked loops–A review
This paper presents a symmetric review of academic and accomplished research endeavors
in the field of Sub-Sampling Phase Locked Loop (SSPLL) design. Adequate emphasis has …
in the field of Sub-Sampling Phase Locked Loop (SSPLL) design. Adequate emphasis has …
Dual-time resolution time-based transceiver for low-power serial interfaces
M Rashdan - Analog Integrated Circuits and Signal Processing, 2017 - Springer
A dual-time resolution differential-time signaling (DTR-DTS) architecture is proposed in this
paper. The number of transmitted bits per symbol in a time-based serial link can be …
paper. The number of transmitted bits per symbol in a time-based serial link can be …
Design and analysis of collective pulse oscillators
P Mukim, A Dalakoti, D McCarthy… - … Transactions on Very …, 2019 - ieeexplore.ieee.org
Collective pulse oscillators (CPOs) are novel designs constructed using pulse regenerative
amplifiers that exhibit time-variant gate delay based on the residual charge from past state …
amplifiers that exhibit time-variant gate delay based on the residual charge from past state …
[PDF][PDF] 一种25 Gbit/s CMOS 自适应判决反馈均衡器
赵文斌， 张长春， 张桄华， 董舒路 - Microelectronics, 2021 - researching.cn
基于65nmCMOS 工艺, 设计了一种25Gbit/s 带有一个无限冲激响应抽头的自适应判决反馈均衡
器. 该均衡器中关键路径采用堆叠式选择器和锁存器组成的半速率预测式结构 …
器. 该均衡器中关键路径采用堆叠式选择器和锁存器组成的半速率预测式结构 …
Hybrid Pulse-Amplitude-Modulation Signaling Scheme and Clock Synthesis for Next Generation Ultra-High-Speed Wire-Line Transmitters
RS Bindiganavile - 2024 - search.proquest.com
High-speed and low-energy data movement is vital in modern High-Performance Computing
(HPC) systems. The bandwidth (BW) for transferring data among different processing …
(HPC) systems. The bandwidth (BW) for transferring data among different processing …
A Controllable KVCO Ring VCO Topology
R Bindiganavile, A Tajalli - 2021 IEEE International Midwest …, 2021 - ieeexplore.ieee.org
A differential ring Voltage Controlled Oscillator (VCO) with a controllable K VCO is
introduced. The capability to control K VCO enables post-fabrication calibration of VCO gain …
introduced. The capability to control K VCO enables post-fabrication calibration of VCO gain …
[图书][B] ADC-based Receivers for Wireline Communication
L Wang - 2019 - search.proquest.com
Power efficient analog to digital converter (ADC) based receivers are desired for wireline
communications as the industry transitions to 4-PAM at data-rates above 50Gb/s. A high …
communications as the industry transitions to 4-PAM at data-rates above 50Gb/s. A high …
A 0.1–1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process
B Zhong, Z Zhu - Journal of Semiconductors, 2016 - iopscience.iop.org
Abstract A 0.1–1.5 GHz, 3.07 pS root mean squares (RMS) jitter, area efficient phase locked
loop (PLL) with multiphase clock outputs is presented in this paper. The size of capacitor in …
loop (PLL) with multiphase clock outputs is presented in this paper. The size of capacitor in …