LEAP: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design
HHK Lee, L Klas, B Mounaim… - 2010 IEEE …, 2010 - ieeexplore.ieee.org
This paper presents a new layout design principle called LEAP which is an acronym for
Layout Design through Error-Aware Transistor Positioning. This principle extends beyond …
Layout Design through Error-Aware Transistor Positioning. This principle extends beyond …
Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation
This paper investigates the impact of terrestrial radiation on soft error (SE) sensitivity along
the very large-scale integration (VLSI) roadmap of bulk, FDSOI and finFET nano-scale …
the very large-scale integration (VLSI) roadmap of bulk, FDSOI and finFET nano-scale …
Neutron-and proton-induced single event upsets for D-and DICE-flip/flop designs at a 40 nm technology node
Neutron-and proton-induced single-event upset cross sections of D-and DICE-Flip/Flops are
analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton …
analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton …
Ionizing Radiation Effectsin Electronics
M Bagatin, S Gerardin - 2016 - api.taylorfrancis.com
There is an invisible enemy that constantly threatens the operation of electronics: ionizing
radiation. From sea level to outer space, ionizing radiation is virtually everywhere. At sea …
radiation. From sea level to outer space, ionizing radiation is virtually everywhere. At sea …
Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes
Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to
transients measured in 130-nm and 90-nm processes. The measured SET widths are …
transients measured in 130-nm and 90-nm processes. The measured SET widths are …
Design techniques to reduce SET pulse widths in deep-submicron combinational logic
OA Amusan, LW Massengill, BL Bhuva… - … on Nuclear Science, 2007 - ieeexplore.ieee.org
Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection
and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET …
and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET …
Mitigation techniques for single-event-induced charge sharing in a 90-nm bulk CMOS process
OA Amusan, LW Massengill, MP Baze… - … on device and …, 2009 - ieeexplore.ieee.org
In this paper, mitigation techniques to reduce the increased SEU cross section associated
with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error …
with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error …
Single-event transient modeling in a 65-nm bulk CMOS technology based on multi-physical approach and electrical simulations
This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and
electrical simulations (CADENCE tool). The method is validated by SET measurements on …
electrical simulations (CADENCE tool). The method is validated by SET measurements on …
Anthology of the development of radiation transport tools as applied to single event effects
This anthology contains contributions from eleven different groups, each developing and/or
applying Monte Carlo-based radiation transport tools to simulate a variety of effects that …
applying Monte Carlo-based radiation transport tools to simulate a variety of effects that …
[图书][B] Radiation effects in semiconductors
K Iniewski - 2018 - taylorfrancis.com
Space applications, nuclear physics, military operations, medical imaging, and especially
electronics (modern silicon processing) are obvious fields in which radiation damage can …
electronics (modern silicon processing) are obvious fields in which radiation damage can …