System and method for data synchronization for a computer architecture for broadband networks

M Suzuoki, T Yamazaki - US Patent 8,434,091, 2013 - Google Patents
(57) ABSTRACT A computer architecture and programming model for high speed
processing over broadband networks are provided. The architecture employs a consistent …

Scalable high performance 3d graphics

M Deering, M Lavelle - US Patent App. 10/394,418, 2004 - Google Patents
A high-speed ring topology. In one embodiment, two base chip types are required: a
“drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have …

Managing a plurality of processors as devices

M Aguilar Jr, MN Day, MR Nutter, JM Stafford - US Patent 7,523,157, 2009 - Google Patents
US PATENT DOCUMENTS system to facilitate a communication between an application
requesting access to a processor and the processor. A device 4,394,727 A 7, 1983 Hoffman …

Scalable high performance 3D graphics

MF Deering, MG Lavelle - US Patent 7,379,067, 2008 - Google Patents
A high-speed ring topology. In one embodiment, two base chip types are required: a
“drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have …

System and method for sharing memory by heterogeneous processors

HP Hofstee, CR Johns, JA Kahle - US Patent 7,321,958, 2008 - Google Patents
2003-10-30 Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …

Reconfigurable integrated circuit device

I Kasama, T Tsuruta, M Nishida - US Patent App. 11/340,871, 2007 - Google Patents
A reconfigurable integrated circuit device which is dynamically constructed to be an arbitrary
operation status based on a configuration data, has a plurality of clusters including operation …

System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment

M Aguilar Jr, MN Day, MR Nutter, J Xenidis - US Patent 7,389,508, 2008 - Google Patents
A system and method for grouping processors is presented. A processing unit (PU) initiates
an application and identifies the application's requirements. The PU assigns one or more …

Asymmetric heterogeneous multi-threaded operating system

M Aguilar Jr, MN Day, MR Nutter, JM Stafford - US Patent 7,516,456, 2009 - Google Patents
4,394,727 A* 7/1983 Hoffman et al............. ZE embodiment, the SPU scheduler may use a
single SPU run 3. Hats al. 2. queue to schedule tasks for the plurality of SPUs or, the SPU …

Client terminal for executing multiplayer application, group forming method, and group forming program

K Yamauchi, Y Iwata, S Matsunaga - US Patent 7,780,533, 2010 - Google Patents
(57) ABSTRACT A given terminal of a plurality of terminals in a network system that also
includes a server apparatus, the terminals respectively corresponding to characters that …

Task manager with stored task definition having pointer to a memory address containing required code data related to the task for execution

JP Bates, PR White, RB Stenson, H Berkey… - US Patent …, 2011 - Google Patents
US PATENT DOCUMENTS 6,003,112 A 12, 1999 Tetrick 6,144,986 A 11, 2000 Silver 6.279,
040 B1 8, 2001 Ma et al. 6,289,369 B1 9/2001 Sundaresan................... TO9, 103 6,295,598 …