This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-
time converter, placed in the feedback path, cancels out the quantization noise introduced …

Whether employed as local oscillators in wireless communications or radar systems, or as
clock generators in data converters, high-performance frequency synthesizers are essential …

This paper presents a low-power high-bit-rate phase modulator based on a digital PLL with
single-bit TDC and two-point injection scheme. At high bit rates, this scheme requires a …

In digital bang-bang phase-locked loops (BBPLLs), both the hard nonlinearity of the phase
detector and the frequency granularity of the digitally controlled oscillator (DCO) can give …

In the last few years, several digital implementations of phase-locked loops (PLLs) have
emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang …

This work introduces an accurate linearized model and phase noise spectral analysis of
digital bang-bang PLLs, that includes both the reference and the digitally-controlled …

This paper presents a digital bang-bang phase-locked loop (DBPLL) that employs automatic
loop gain control and loop latency reduction techniques to enhance the jitter performance …

A 0.3–1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller
(ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The …

We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency
domain that is complete and self-consistent. It enables the manual design of frequency …

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates
for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase …