[HTML][HTML] Uncertainty in runtime verification: A survey

R Taleb, S Hallé, R Khoury - Computer Science Review, 2023 - Elsevier
Runtime Verification can be defined as a collection of formal methods for studying the
dynamic evaluation of execution traces against formal specifications. Aside from creating a …

Distributed model predictive control for probabilistic signal temporal logic specifications

T Yang, Y Zou, S Li, Y Yang - IEEE Transactions on Automation …, 2023 - ieeexplore.ieee.org
This paper proposes a distributed model predictive control (DMPC) for a class of discrete-
time stochastic multi-agent systems subject to partially coupled temporal logic tasks. For …

STL robustness risk over discrete-time stochastic processes

L Lindemann, N Matni… - 2021 60th IEEE …, 2021 - ieeexplore.ieee.org
We present a framework to interpret signal temporal logic (STL) formulas over discrete-time
stochastic processes in terms of the induced risk. Each realization of a stochastic process …

Risk of stochastic systems for temporal logic specifications

L Lindemann, L Jiang, N Matni, GJ Pappas - ACM Transactions on …, 2023 - dl.acm.org
The wide availability of data coupled with the computational advances in artificial
intelligence and machine learning promise to enable many future technologies such as …

Shield Synthesis for LTL Modulo Theories

A Rodriguez, G Amir, D Corsi, C Sanchez… - arXiv preprint arXiv …, 2024 - arxiv.org
In recent years, Machine Learning (ML) models have achieved remarkable success in
various domains. However, these models also tend to demonstrate unsafe behaviors …

Online event recognition over noisy data streams

P Mantenoglou, A Artikis, G Paliouras - International Journal of …, 2023 - Elsevier
Composite event recognition (CER) systems process streams of sensor data and infer
composite events of interest by means of pattern matching. Data uncertainty is frequent in …

Stochastic robustness interval for motion planning with signal temporal logic

RB Ilyes, QH Ho, M Lahijanian - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
In this work, we present a novel robustness measure for continuous-time stochastic
trajectories with respect to Signal Temporal Logic (STL) specifications. We show the …

Model predictive robustness of signal temporal logic predicates

Y Lin, H Li, M Althoff - IEEE Robotics and Automation Letters, 2023 - ieeexplore.ieee.org
The robustness of signal temporal logic not only assesses whether a signal adheres to a
specification but also provides a measure of how much a formula is fulfilled or violated. The …

Runtime verification under access restrictions

R Taleb, R Khoury, S Hallé - 2021 IEEE/ACM 9th International …, 2021 - ieeexplore.ieee.org
We define a logical framework that permits runtime verification to take place when a monitor
has incomplete or uncertain information about the underlying trace. Uncertainty is modeled …

Signal temporal logic synthesis as probabilistic inference

KMB Lee, C Yoo, R Fitch - 2021 IEEE International Conference …, 2021 - ieeexplore.ieee.org
We reformulate the signal temporal logic (STL) synthesis problem as a maximum a-
posteriori (MAP) inference problem. To this end, we introduce the notion of random STL …