Digitally synthesized stochastic flash ADC using only standard digital cells
S Weaver, B Hershberg… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC
entirely from Verilog code and a standard digital library. An analog comparator is introduced …
entirely from Verilog code and a standard digital library. An analog comparator is introduced …
A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS
A Shikata, R Sekimoto, T Kuroda… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
This paper presents an extremely low-voltage operation and power efficient successive-
approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is …
approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is …
An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells
An all-digital programmable and reconfigurable stochastic analog-to-digital converter (ADC)
is presented in this work. This ADC directly benefits from scaling by using only digital gates …
is presented in this work. This ADC directly benefits from scaling by using only digital gates …
A 0.5-V fully synthesizable SAR ADC for on-chip distributed waveform monitors
This paper presents a fully synthesizable successive-approximation-register (SAR) analog-
to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system …
to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system …
A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS
P Nuzzo, C Nani, C Armiento… - … on Circuits and …, 2011 - ieeexplore.ieee.org
A successive approximation analog-to-digital converter (ADC) architecture is presented that
programs its comparator threshold at runtime to approximate the input signal via binary …
programs its comparator threshold at runtime to approximate the input signal via binary …
Bulk voltage trimming offset calibration for high-speed flash ADCs
A bulk voltage trimming offset calibration technique is presented for flash analog-to-digital
converters (ADCs). Offset calibration is achieved by digitally adjusting the bulk voltages of …
converters (ADCs). Offset calibration is achieved by digitally adjusting the bulk voltages of …
Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons
This work is focused on the performance of three different standard-cell-based comparator
topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in …
topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in …
A 4-bit, 1.6 GS/s low power flash ADC, based on offset calibration and segmentation
M Chahardori, M Sharifkhani… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which
masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced …
masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced …
A stochastic flash analog-to-digital converter linearized by reference swapping
MK Jeon, WJ Yoo, CG Kim, C Yoo - IEEE Access, 2017 - ieeexplore.ieee.org
The linearity of a stochastic flash analog-to-digital converter (ADC) with two groups of
comparators is improved by reference swapping. If the input offset of a comparator is larger …
comparators is improved by reference swapping. If the input offset of a comparator is larger …
Reliable measurement using unreliable binary comparisons
We consider the problem of measuring a physical quantity of interest, such as a voltage,
pressure, or density, by comparing it against several references whose values are not …
pressure, or density, by comparing it against several references whose values are not …