This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …

Test data compression consists of test vector compression on the input side and response,
compaction on the output side. This vector compression has been an active area of …

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

Advances in semiconductor process and design technology enable the design of complex
system chips. Traditional IC design in which every circuit is designed from scratch and reuse …

Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …

We consider active data selection and test point rejection strategies for Gaussian process
regression based on the variance of the posterior over target values. Gaussian process …

Combinational circuits implemented with exclusive-or gates are used for on-chip generation
of deterministic test patterns from compressed seeds. Unlike major test compression …

One of the major challenges in testing a system-on-a-chip is dealing with the large volume of
test data. To reduce the volume of test data, several test data compression techniques have …

We present a selective encoding method that reduces test data volume and test application
time for scan testing of intellectual property (IP) cores. This method encodes the slices of test …

This paper extends the reconfigurable shared scan-in architecture (RSSA) to provide
additional ability to change values on the scan configuration signals (scan enable signals) …