A method for data transfer includes transmitting a sequence of data packets, including at
least a first packet and a second packet transmitted subsequently to the first packet, from a …

Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …

Subject matter disclosed herein relates to arrangements and techniques for sending
messages directly among processing cores and directly among co-processors over a …

Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …

The present disclosure relates to automatic sizing of NoC channel buffers of one or more
virtual channels to optimize NoC design, SoC design, and to meet defined performance …

A memory extensible chip (200) is provided. The chip (200) includes a substrate (240), and
a processor (230), a first memory module set (210), and a second memory module set (220) …

Example implementations are directed to more efficiently delivering a multicast message to
multiple destination components from a source component. Multicast environment is …

The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …

certain devices may be configured in a System-in-Package (SiP) form, in which a
programmable device, such as a field programmable gate array (FPGA) is coupled to a …

A multi-chip structure that implements a configurable Network-on-Chip (NoC) for
communication between chips is described herein. In an example, an apparatus includes a …