A 0.1–1.5 GHz 8-bit inverter-based digital-to-phase converter using harmonic rejection
This paper presents a digital-to-phase converter (DPC) with 8-bits of resolution and a wide
frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to …
frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to …
A 50–64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65 nm CMOS technology
This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap
equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the …
equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the …
A sub-2 W 39.8–44.6 Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40 nm CMOS
B Raghavan, D Cui, U Singh, H Maarefi… - IEEE journal of solid …, 2013 - ieeexplore.ieee.org
A 39.8-44.6 Gb/s transmitter and receiver chipset designed in 40 nm CMOS is presented.
The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side …
The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side …
Toward millimeter-wave DACs: Challenges and opportunities
As line widths in emerging III-V technologies approaching that of modern CMOS, the
conception of high performance mixed signal designs such as digital to analog converters …
conception of high performance mixed signal designs such as digital to analog converters …
A multichannel serial link receiver with dual-loop clock-and-data recovery and channel equalization
N Kalantari, JF Buckwalter - … on Circuits and Systems I: Regular …, 2013 - ieeexplore.ieee.org
This paper presents a four channel receiver for high-speed signal conditioning. Each
channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with …
channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with …
A dual-channel 23-Gbps CMOS transmitter/receiver chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK optical transmission
D Cui, B Raghavan, U Singh, A Vasani… - IEEE journal of solid …, 2012 - ieeexplore.ieee.org
This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS
process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical …
process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical …
A novel low gate-count pipeline topology with multiplexer-flip-flops for serial link
This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost
solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that …
solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that …
40-Gb/s 0.7-V 2: 1 MUX and 1: 2 DEMUX with transformer-coupled technique for SerDes interface
FT Chen, JM Wu, MCF Chang - IEEE Transactions on Circuits …, 2015 - ieeexplore.ieee.org
This paper explores the use of transformer-coupled (TC) technique for the 2: 1 MUX and the
1: 2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely …
1: 2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely …
A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard
G Chen, M Gong, D Fu, J Zhang - IEICE Electronics Express, 2018 - jstage.jst.go.jp
A 12.5 Gbps continuous-time linear equalizer circuit (CTLE) constructed with two stage
equalizer, three stages of limiting amplifier and designed in 55nm CMOS technology for high …
equalizer, three stages of limiting amplifier and designed in 55nm CMOS technology for high …
Clock multiplication and distribution
WW Walker, P Thachile, N Nedovic - US Patent 9,348,358, 2016 - Google Patents
A clock multiplication and distribution system includes a first phase-lock-loop circuit, a
second phase-lock-loop circuit, and a clock distribution network that electrically couples the …
second phase-lock-loop circuit, and a clock distribution network that electrically couples the …