A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …

Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital
controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital …

US10171089B2 - PVT-free calibration function using a doubler circuit for TDC resolution in
ADPLL applications - Google Patents US10171089B2 - PVT-free calibration function using …

A regulator system includes a multi-bit detector system and a multi-cell charge/discharge
circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of …

A phase-locked loop circuit, a phase converter module thereof and a phase-locked
controlling method are disclosed herein. The phase converter module is suitable for a phase …

2019-10-30 Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD …

BACKGROUND A phase-locked loop (PLL) is an electronic control system that generates an
oscillating signal having a fixed phase rela tionship (eg, synchronized or having a fixed gap) …

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …

A circuit for measuring clock jitter includes: an internal signal generator configured to
generate an internal clock signal and a single pulse signal, respectively synchronized with …

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …