Field programmable gate array applications—A scientometric review
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device
that can be configured by a customer after manufacturing to perform from a simple logic gate …
that can be configured by a customer after manufacturing to perform from a simple logic gate …
Recent advances on HEVC inter-frame coding: From optimization to implementation and beyond
High Efficiency Video Coding (HEVC) has doubled the video compression ratio with
equivalent subjective quality as compared to its predecessor H. 264/AVC. The significant …
equivalent subjective quality as compared to its predecessor H. 264/AVC. The significant …
Power-efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design
Sum of absolute differences (SAD) calculation is one of the most time-consuming operations
of video encoders compatible with the high efficiency video coding standard. SAD hardware …
of video encoders compatible with the high efficiency video coding standard. SAD hardware …
Optimisation of HEVC motion estimation exploiting SAD and SSD GPU‐based implementation
The new High‐Efficiency Video Coding (HEVC) standard doubles the video compression
ratio compared to the previous H. 264/AVC at the same video quality and without any …
ratio compared to the previous H. 264/AVC at the same video quality and without any …
Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder
E Alcocer, R Gutierrez, O Lopez-Granado… - Journal of Real-Time …, 2019 - Springer
Abstract High-Efficiency Video Coding (HEVC) was developed to improve its predecessor
standard, H264/AVC, by doubling its compression efficiency. As in previous standards …
standard, H264/AVC, by doubling its compression efficiency. As in previous standards …
A hardware-oriented IME algorithm for HEVC and its hardware implementation
Y Fan, L Huang, B Hao, X Zeng - IEEE Transactions on Circuits …, 2017 - ieeexplore.ieee.org
High Efficiency Video Coding (HEVC), the latest video coding standard, aims to provide
coding performance that is much superior to that of its predecessor, H. 264, especially for …
coding performance that is much superior to that of its predecessor, H. 264, especially for …
Energy-efficient motion estimation with approximate arithmetic
Energy efficiency has become a primary concern in the design of multimedia digital systems,
particularly when targeting mobile devices. Approximate computing is a highly promising …
particularly when targeting mobile devices. Approximate computing is a highly promising …
Real-time motion estimation diamond search algorithm for the new high efficiency video coding on FPGA
High efficiency video coding (HEVC) is the latest video coding standard aimed to replace the
H. 264/AVC standard according to its high coding performance, which allows it to be mostly …
H. 264/AVC standard according to its high coding performance, which allows it to be mostly …
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding
The sum of absolute difference (SAD) calculation is one of the most computing-intensive
operations in video encoders compatible with recent standards, such as high-efficiency …
operations in video encoders compatible with recent standards, such as high-efficiency …
Efficient sum of absolute difference computation on FPGAs
M Kumm, M Kleinlein, P Zipf - 2016 26th International …, 2016 - ieeexplore.ieee.org
An improved architecture for efficiently computing the sum of absolute differences (SAD) on
FPGAs is proposed in this work. It is based on a configurable adder/subtractor …
FPGAs is proposed in this work. It is based on a configurable adder/subtractor …