In this paper we propose μ RV32 (MicroRV32) an open source RISC-V platform for
education and research. μ RV32 integrates several peripherals alongside a configurable 32 …

Tile-based many-core architectures are extensively used in modern system-on-chip designs
to achieve scalable computing performance with adequate energy efficiency. Heterogeneity …

This paper describes two different approaches to emulate an Ethernet communication link
between a host computer and a RISC-V multiprocessor system running on a FPGA …

This work presents Chronos-V, a Many-Core System-on-Chip (MCSoC) that adopts abstract
hardware modeling, executing the FreeRTOS Operating System (OS) at each processing …

The increasing complexity of System-on-Chip (SoC) architectures requires efficient data
transfer and integration of multiple processing units. Network-on-Chip (NoC) technology is …

Multi-/many-core heterogeneous architectures are shaping current and upcoming
generations of compute-centric platforms which are widely used starting from mobile and …

Simulation of Computing Systems plays a crucial role in state-of-the-art design validation
and optimization methodologies. Traditionally, Register Transfer-Level (RTL) simulation is a …

A. Kamaleldin, D. Göhringer: AGILER: Adaptive Heterogeneous Tile-Based Many-Core
Architecture for RISC-V Processors a growing capacity of heterogeneous compute elements …