Rvfpga: Using a risc-v core targeted to an fpga in computer architecture education

SL Harris, D Chaver, L Piñuel… - … Conference on Field …, 2021 - ieeexplore.ieee.org
RISC-V FPGA, also written RVfpga, is a set of two freely available courses developed by the
authors and Imagination Technologies that enable users to understand and use the RISC-V …

Simplifi: hardware simulation of embedded software fault attacks

J Grycel, P Schaumont - Cryptography, 2021 - mdpi.com
Fault injection simulation on embedded software is typically captured using a high-level fault
model that expresses fault behavior in terms of programmer-observable quantities. These …

Vertically integrated computing labs using open-source hardware generators and cloud-hosted fpgas

A Amid, A Ou, K Asanović, YS Shao… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
The design of computing systems has changed dramatically over the past decade, but most
courses in advanced computer architecture remain unchanged. Computer architecture …

Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers

P Jamieson, H Le, N Martin, T McGrew, Y Qian… - Journal of Low Power …, 2022 - mdpi.com
With the growing popularity of RISC-V and various open-source released RISC-V
processors, it is now possible for computer engineers students to explore this simple and …

Mind the gap: Bridging verilog and computer architecture

F Passe, M Canesche, OPV Neto… - … on Circuits and …, 2020 - ieeexplore.ieee.org
We present an approach to teach RISC processor design for an undergraduate computer
architecture course specifically aimed to reduce the gap between a high-level datapath …

Digital Teaching an Embedded Systems Course by Using Simulators

M Koenig, R Rasch - 2021 ACM/IEEE Workshop on Computer …, 2021 - ieeexplore.ieee.org
In this paper, we discuss how an embedded system course was transferred from classroom
teaching to digital teaching using simulation tools instead of physical embedded systems …

RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA

SA Zekany, J Tan, JA Connelly… - Proceedings of the 52nd …, 2021 - dl.acm.org
We describe our experience teaching an undergraduate capstone (and elective graduate
course) in computer architecture with a semester-long project in which teams of five students …

An FPGA Integrated 2D Graphic Processor for Enhanced Digital Design and Computer Architecture Education

GSB Alves, JCN Bittencourt… - … Revista Iberoamericana de …, 2024 - ieeexplore.ieee.org
In the rapidly evolving domain of technology education, the integration of digital systems and
computer architecture into a unified academic curriculum has become increasingly …

RISCALAR: A Cycle-Approximate, Parametrisable RISC-V Microarchitecture Explorer & Simulator

J Mendes, RC Panicker - 2024 IEEE International Symposium …, 2024 - ieeexplore.ieee.org
Riscalar is a highly parameterisable, extensible, and modular computer architecture
simulation tool designed for the RISC-V ISA. The ability of Riscalar to explore a large design …

LY86-64: a Web-based Simulator for the Y86-64 PIPE Architecture

CB Ly, C Norris - Proceedings of the 2022 ACM Southeast Conference, 2022 - dl.acm.org
Computer architecture simulators play an important role in education and in advancing
improved architecture designs. For Computer Science students, implementing an …