{ScatterCache}: thwarting cache attacks via cache set randomization
Cache side-channel attacks can be leveraged as a building block in attacks leaking secrets
even in the absence of software bugs. Currently, there are no practical and generic …
even in the absence of software bugs. Currently, there are no practical and generic …
Masked accelerators and instruction set extensions for post-quantum cryptography
T Fritzmann, M Van Beirendonck… - IACR Transactions …, 2021 - lirias.kuleuven.be
Side-channel attacks can break mathematically secure cryptographic systems leading to a
major concern in applied cryptography. While the cryptanalysis and security evaluation of …
major concern in applied cryptography. While the cryptanalysis and security evaluation of …
The speedy family of block ciphers-engineering an ultra low-latency cipher from gate level for secure processor architectures
We introduce SPEEDY, a family of ultra low-latency block ciphers. We mix engineering
expertise into each step of the cipher's design process in order to create a secure encryption …
expertise into each step of the cipher's design process in order to create a secure encryption …
Glitch-resistant masking revisited: Or why proofs in the robust probing model are needed
Implementing the masking countermeasure in hardware is a delicate task. Various solutions
have been proposed for this purpose over the last years: we focus on Threshold …
have been proposed for this purpose over the last years: we focus on Threshold …
Modulonet: Neural networks meet modular arithmetic for efficient hardware masking
Intellectual Property (IP) thefts of trained machine learning (ML) models through side-
channel attacks on inference engines are becoming a major threat. Indeed, several recent …
channel attacks on inference engines are becoming a major threat. Indeed, several recent …
Generic low-latency masking in hardware
In this work, we introduce a generalized concept for low-latency masking that is applicable to
any implementation and protection order, and (in its most extreme form) does not require on …
any implementation and protection order, and (in its most extreme form) does not require on …
Low-latency hardware masking with application to AES
During the past two decades there has been a great deal of research published on masked
hardware implementations of AES and other cryptographic primitives. Unfortunately, many …
hardware implementations of AES and other cryptographic primitives. Unfortunately, many …
Second-order SCA security with almost no fresh randomness
AR Shahmirzadi, A Moradi - IACR Transactions on Cryptographic …, 2021 - tches.iacr.org
Masking schemes are among the most popular countermeasures against Side-Channel
Analysis (SCA) attacks. Realization of masked implementations on hardware faces several …
Analysis (SCA) attacks. Realization of masked implementations on hardware faces several …
Low-latency keccak at any arbitrary order
Correct application of masking on hardware implementation of cryptographic primitives
necessitates the instantiation of registers in order to achieve the non-completeness …
necessitates the instantiation of registers in order to achieve the non-completeness …
A lightweight implementation of saber resistant against side-channel attacks
The field of post-quantum cryptography aims to develop and analyze algorithms that can
withstand classical and quantum cryptanalysis. The NIST PQC standardization process, now …
withstand classical and quantum cryptanalysis. The NIST PQC standardization process, now …