Junctionless transistors: State-of-the-art
A Nowbahari, A Roy, L Marchetti - Electronics, 2020 - mdpi.com
Recent advances in semiconductor technology provide us with the resources to explore
alternative methods for fabricating transistors with the goal of further reducing their sizes to …
alternative methods for fabricating transistors with the goal of further reducing their sizes to …
Probing charge traps at the 2D semiconductor/dielectric interface
The family of 2-dimensional (2D) semiconductors is a subject of intensive scientific research
due to their potential in next-generation electronics. While offering many unique properties …
due to their potential in next-generation electronics. While offering many unique properties …
Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm
In this letter, we report the performance of high-κ/metal gate nanowire (NW) transistors
without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length …
without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length …
Device and circuit performance estimation of junctionless bulk FinFETs
MH Han, CY Chang, HB Chen… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are
compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum …
compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum …
p-Type trigate junctionless nanosheet MOSFET: analog/RF, linearity, and circuit analysis
BS Vakkalakula, N Vadthiya - … Journal of Solid State Science and …, 2021 - iopscience.iop.org
Abstract Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors
(MOSFETs) are realized as an outstanding structure to obtain better area scaling and power …
(MOSFETs) are realized as an outstanding structure to obtain better area scaling and power …
Electro-thermal characteristics of junctionless nanowire gate-all-around transistors using compact thermal conductivity model
The electrothermal performance of a junctionless nanowire [JL-nanowire (NW)] gate-all-
around (GAA) transistors under self-heating effect (SHE) is examined for sub-5 nm …
around (GAA) transistors under self-heating effect (SHE) is examined for sub-5 nm …
A vertically integrated junctionless nanowire transistor
A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of
vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure …
vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure …
Deep learning algorithms for the work function fluctuation of random nanosized metal grains on gate-all-around silicon nanowire MOSFETs
Device simulation has been explored and industrialized for over 40 years; however, it still
requires huge computational cost. Therefore, it can be further advanced using deep learning …
requires huge computational cost. Therefore, it can be further advanced using deep learning …
Thermal conductivity model to analyze the thermal implications in nanowire FETs
In this article, a thermal conductivity () model is proposed (ie, dependent on the temperature,
thickness, and doping concentration) for investigating the thermal behavior of silicon-on …
thickness, and doping concentration) for investigating the thermal behavior of silicon-on …
Performance analysis of gate electrode work function variations in double-gate junctionless FET
With inherent structural simplicity due to the omission of ultrasteep pn junctions, the
conventional junctionless FET can be used as a barrier-controlled device with low OFF …
conventional junctionless FET can be used as a barrier-controlled device with low OFF …