An optimum loop gain tracking all-digital PLL using autocorrelation of bang–bang phase-frequency detection
S Jang, S Kim, SH Chu, GS Jeong… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
An all-digital phase-locked loop with a bang-bang phase-frequency detector (BBPFD) that
tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the …
tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the …
State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS
RB Staszewski - IEEE Transactions on Circuits and Systems I …, 2011 - ieeexplore.ieee.org
The past several years have successfully brought all-digital techniques to the RF frequency
synthesis, which could arguably be considered one of the last strong bastions of the …
synthesis, which could arguably be considered one of the last strong bastions of the …
Spur-free multirate all-digital PLL for mobile phones in 65 nm CMOS
RB Staszewski, K Waheed, F Dulger… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring
phase/frequency modulation capability. While the ADPLL approach has already proven its …
phase/frequency modulation capability. While the ADPLL approach has already proven its …
Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature]
Fast settling phase locked loops (PLLs) play a pivotal role in many applications requiring
rapid attainment of a stable frequency and phase. In modern communication standards …
rapid attainment of a stable frequency and phase. In modern communication standards …
A comprehensive review: ultra-low power all-digital phase-locked loop RF transceivers for biomedical monitoring applications
This paper comprehensively reviews the evolution and latest advancement of ultra-low All-
Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical …
Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical …
A fast-locking all-digital phase-locked loop with dynamic loop bandwidth adjustment
JM Lin, CY Yang - IEEE Transactions on Circuits and Systems I …, 2015 - ieeexplore.ieee.org
A fast-locking all-digital phase-locked loop (ADPLL) including a fast-locking unit, a multi-
level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC) …
level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC) …
A low-power wide dynamic-range current readout circuit for ion-sensitive FET sensors
This paper presents an amplifier-less and digital-intensive current-to-digital converter for ion-
sensitive FET sensors. Capacitance on the input node is utilized as a residue accumulator …
sensitive FET sensors. Capacitance on the input node is utilized as a residue accumulator …
A 3.9 mW Bluetooth low-energy transmitter using all-digital PLL-based direct FSK modulation in 55 nm CMOS
This paper presents a low-power frequency-shift keying (FSK) transmitter (TX) with an all-
digital phase locked loop (ADPLL) based on direct modulation for use in Bluetooth low …
digital phase locked loop (ADPLL) based on direct modulation for use in Bluetooth low …
A 2.4–3.6-GHz wideband subharmonically injection-locked PLL with adaptive injection timing alignment technique
This paper proposes a wideband subharmonically injection-locked PLL (SILPLL) with
adaptive injection timing alignment technique. The SILPLL includes three main circuit …
adaptive injection timing alignment technique. The SILPLL includes three main circuit …
A 2.7 mW/channel 48–1000 MHz direct sampling full-band cable receiver
J Wu, G Cusmai, A Wei-Te Chou… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is
presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS …
presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS …