Since line-end roughness (LER) has been reported to be of the order of several nanometers
and to not decrease as the device shrinks, it has evolved as a critical problem in sub-45-nm …

Design rules have been the primary contract between technology developers and designers
and are likely to remain so to preserve abstractions and productivity. While current …

As the transistors are scaled down, undesirable performance mismatch in identically
designed transistors increases and hence causes greater impact on circuit performance and …

Design rules have been the primary contract between technology and design and are likely
to remain so to preserve abstractions and productivity. While current approaches for defining …

Lithographic wavelength of 193 nm has been used for past few generations of patterning
and is likely to remain in use for next few technology generations (at least till 28 nm …

Standard cells are fundamental circuit building blocks designed at very early design stages.
Nanometer standard cells are prone to lithography proximity and process variations. How to …

Imperfect lithographic patterning leads to nonrectangular polysilicon and diffusion layers.
Though electrical modeling of polysilicon rounding has received much attention, same is not …

With the increased need for low power applications, designers are being forced to employ
circuit optimization methods that make tradeoffs between performance and power. In this …

Line-end pullback is a major source of patterning problems in low-k 1 lithography.
Lithographers have been well-served by geometric metrics such as critical dimension (CD) …

In this paper, we investigate electrical effects of transistor layout shape (both in the channel
and diffusion) on the performance and leakage current. Through layout optimization …