Exploring the performance of 3-D nanosheet FET in inversion and junctionless modes: Device and circuit-level analysis and comparison

VB Sreenivasulu, AK Neelam, SR Kola, J Singh… - IEEE …, 2023 - ieeexplore.ieee.org
In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and
junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In …

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

P Praveen, RK Singh - ACM Transactions on Design Automation of …, 2023 - dl.acm.org
Power dissipation is considered one of the important issues in low power Very-large-scale
integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub …

Experimental characterization of multitone EM immunity of integrated oscillators under thermal stress

QM Khan, L Devaraj, R Perdriau, AR Ruddle… - Ieee …, 2022 - ieeexplore.ieee.org
The reliable operation of an integrated circuit can be affected by environmental changes,
such as of multiple frequency electromagnetic (EM) disturbances and temperature …

Design and Parametric Analysis of 6T SRAM Using 180nm and 45nm Technology

S Bagali, B Sravani, B Kavya… - 2023 International …, 2023 - ieeexplore.ieee.org
SRAM has high storage density and fast access time which made it a crucial component in
many VLSI chips. Due to their simplicity of usage and minimal standby leakage, SRAMs are …

Synaptic MIS Silicon Nitride Resistance Switching Memory Cells on SOI Substrate

AE Mavropoulis, N Vasileiadis… - 2023 IEEE 23rd …, 2023 - ieeexplore.ieee.org
In this work, the comparison of resistive memory MIS single-cells without selector (1R),
having silicon nitride as switching dielectric, fabricated on SOI and bulk Si wafers is …