Toward smart embedded systems: A self-aware system-on-chip (soc) perspective

N Dutt, A Jantsch, S Sarma - ACM Transactions on Embedded …, 2016 - dl.acm.org
Embedded systems must address a multitude of potentially conflicting design constraints
such as resiliency, energy, heat, cost, performance, security, etc., all in the face of highly …

Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability

H Hong, J Lim, H Lim, S Kang - ACM Computing Surveys (CSUR), 2015 - dl.acm.org
Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling
and increasing temperatures due to growing power density are threatening lifetime …

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

K Bhardwaj, K Chakraborty, S Roy - Proceedings of the 49th Annual …, 2012 - dl.acm.org
Continuous technology scaling has made aging mechanisms such as Negative Bias
Temperature Instability (NBTI) and electromigration primary concerns in Network-on-Chip …

Unified reliability estimation and management of NoC based chip multiprocessors

AY Yamamoto, C Ababei - Microprocessors and Microsystems, 2014 - Elsevier
We present a new architecture level unified reliability evaluation methodology for chip
multiprocessors (CMPs). The proposed reliability estimation (REST) is based on a Monte …

An MILP-based aging-aware routing algorithm for NoCs

K Bhardwaj, K Chakraborty… - 2012 Design, Automation & …, 2012 - ieeexplore.ieee.org
Network-on-Chip (NoC) architectures have emerged as a better replacement of the
traditional bus-based communication in the many-core era. However, continuous technology …

Method and system for extending the lifetime of multi-core integrated circuit devices

RIMP Meijer, G Al-Kadi - US Patent 9,488,998, 2016 - Google Patents
Embodiments of a method and system are disclosed. One embodiment of an integrated
circuit device is disclosed. The integrated circuit device includes first and second processor …

Nbti mitigation in microprocessor designs

S Corbetta, W Fornaciari - Proceedings of the great lakes symposium on …, 2012 - dl.acm.org
Negative-Bias Temperature Instability seriously affects nanoscale circuits reliability and
performance. Continuous stress and increasing operating temperatures lead to device …

Workload capacity considering NBTI degradation in multi-core systems

J Sun, R Lysecky, K Shankar, A Kodi… - 2010 15th Asia and …, 2010 - ieeexplore.ieee.org
As device feature sizes continue to shrink, long-term reliability such as Negative Bias
Temperature Instability (NBTI) leads to low yields and short mean-time-to-failure (MTTF) in …

Investigation of DVFS based dynamic reliability management for chip multiprocessors

MG Moghaddam, A Yamamoto… - … Conference on High …, 2015 - ieeexplore.ieee.org
We investigate dynamic voltage and frequency scaling (DVFS) as a mechanism for dynamic
reliability management (DRM) of chip multiprocessors (CMPs). The proposed DRM scheme …

VAWOM: Temperature and process variation aware wearout management in 3D multicore architecture

H Tajik, H Homayoun, N Dutt - Proceedings of the 50th Annual Design …, 2013 - dl.acm.org
Three dimensional (3D) integration attempts to address challenges and limitations of new
technologies such as interconnect delay and power consumption. However, high power …