A survey of research into mixed criticality systems

A Burns, RI Davis - ACM Computing Surveys (CSUR), 2017 - dl.acm.org
This survey covers research into mixed criticality systems that has been published since
Vestal's seminal paper in 2007, up until the end of 2016. The survey is organised along the …

[PDF][PDF] Mixed criticality systems-a review

A Burns, R Davis - … of Computer Science, University of York …, 2013 - www-users.york.ac.uk
This review covers research on the topic of mixed criticality systems that has been published
since Vestal's 2007 paper. It covers the period up to end of 2021. The review is organised …

A survey of techniques for reducing interference in real-time applications on multicore platforms

T Lugo, S Lozano, J Fernández, J Carretero - IEEE Access, 2022 - ieeexplore.ieee.org
This survey reviews the scientific literature on techniques for reducing interference in real-
time multicore systems, focusing on the approaches proposed between 2015 and 2020. It …

Attacking the one-out-of-m multicore problem by combining hardware management with mixed-criticality provisioning

N Kim, BC Ward, M Chisholm, JH Anderson… - Real-Time …, 2017 - Springer
The multicore revolution is having limited impact in safety-critical application domains. A key
reason is the “one-out-of-m” problem: when validating real-time constraints on an m-core …

Analysis of memory-contention in heterogeneous cots mpsocs

M Hassan, R Pellizzoni - … on Real-Time Systems (ECRTS 2020), 2020 - drops.dagstuhl.de
Abstract Multiple-Processors Systems-on-Chip (MPSoCs) provide an appealing platform to
execute Mixed Criticality Systems (MCS) with both time-sensitive critical tasks and …

Bounding dram interference in cots heterogeneous mpsocs for mixed criticality systems

M Hassan, R Pellizzoni - IEEE Transactions on Computer-Aided …, 2018 - ieeexplore.ieee.org
Commercial off-the-shelf (COTS) heterogeneous multiple processors systems-on-chip
(MPSoCs) are appealing platforms for emerging mixed criticality systems (MCSs). To satisfy …

Designing predictable cache coherence protocols for multi-core real-time systems

AM Kaushik, M Hassan, H Patel - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This article addresses the challenge of allowing simultaneous and predictable accesses to
shared data on multi-core systems. We propose a collection of predictable cache coherence …

Reconciling the tension between hardware isolation and data sharing in mixed-criticality, multicore systems

M Chisholm, N Kim, BC Ward… - 2016 IEEE Real …, 2016 - ieeexplore.ieee.org
Recent work involving a mixed-criticality framework called MC2 has shown that, by
combining hardware-management techniques and criticality-aware task provisioning …

Criticality-and requirement-aware bus arbitration for multi-core mixed criticality systems

M Hassan, H Patel - 2016 IEEE Real-Time and Embedded …, 2016 - ieeexplore.ieee.org
This work presents CArb, an arbiter for controlling accesses to the shared memory bus in
multi-core mixed criticality systems. CArb is a requirement-aware arbiter that optimally …

Holistic resource allocation for multicore real-time systems

M Xu, LTX Phan, HY Choi, Y Lin, H Li… - 2019 IEEE Real-Time …, 2019 - ieeexplore.ieee.org
This paper presents CaM, a holistic cache and memory bandwidth resource allocation
strategy for multicore real-time systems. CaM is designed for partitioned scheduling, where …