SkippyNN: An embedded stochastic-computing accelerator for convolutional neural networks
Employing convolutional neural networks (CNNs) in embedded devices seeks novel low-
cost and energy efficient CNN accelerators. Stochastic computing (SC) is a promising low …
cost and energy efficient CNN accelerators. Stochastic computing (SC) is a promising low …
Fault-tolerant spike routing algorithm and architecture for three dimensional NoC-based neuromorphic systems
TH Vu, OM Ikechukwu, AB Abdallah - IEEE Access, 2019 - ieeexplore.ieee.org
Neuromorphic computing systems are an emerging field that takes its inspiration from the
biological neural architectures and computations inside the mammalian nervous system …
biological neural architectures and computations inside the mammalian nervous system …
Comprehensive analytic performance assessment and K-means based multicast routing algorithm and architecture for 3D-NoC of spiking neurons
Spiking neural networks (SNNs) are artificial neural network models that more closely mimic
biological neural networks. In addition to neuronal and synaptic state, SNNs incorporate the …
biological neural networks. In addition to neuronal and synaptic state, SNNs incorporate the …
Reconfigurable network-on-chip for 3D neural network accelerators
A Firuzan, M Modarressi… - 2018 Twelfth IEEE …, 2018 - ieeexplore.ieee.org
Parallel hardware accelerators for large-scale neural networks typically consist of several
processing nodes, arranged as a multi-or many-core system-on-chip, connected by a …
processing nodes, arranged as a multi-or many-core system-on-chip, connected by a …
A NoC-based simulator for design and evaluation of deep neural networks
KCJ Chen, M Ebrahimi, TY Wang, YC Yang… - Microprocessors and …, 2020 - Elsevier
The astonishing development in the field of artificial neural networks (ANN) has brought
significant advancement in many application domains, such as pattern recognition, image …
significant advancement in many application domains, such as pattern recognition, image …
Neuronlink: An efficient chip-to-chip interconnect for large-scale neural network accelerators
S Xiao, Y Guo, W Liao, H Deng, Y Luo… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
Large-scale neural network (NN) accelerators typically consist of several processing nodes,
which could be implemented as a multi-or many-core chip and organized via a network-on …
which could be implemented as a multi-or many-core chip and organized via a network-on …
SpiCS-Net: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural Networks
Spiking Recurrent Neural Networks (SRNNs) present an alternative computing paradigm to
traditional von Neumann computing in the post-Moore's law era because they omit the …
traditional von Neumann computing in the post-Moore's law era because they omit the …
A survey of machine learning for Network-on-Chips
X Zhang, D Dong, C Li, S Wang, L Xiao - Journal of Parallel and Distributed …, 2024 - Elsevier
Abstract The popularity of Machine Learning (ML) has extended to numerous disciplines,
including the domain of Network-on-chips (NoCs), leading to a consequential impact …
including the domain of Network-on-chips (NoCs), leading to a consequential impact …
Design model of a twisted and folded Clos network with multi-step grouped intermediate switches guaranteeing admissible blocking probability
A future data center network is expected to be constructed by a Clos network consisting of
optical-circuit switches to deal with traffic growth. A previous model addressed a Clos …
optical-circuit switches to deal with traffic growth. A previous model addressed a Clos …
Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs
In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a
promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and …
promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and …