Techniques for probabilistic dynamic random access memory row repair
JH Crawford, BS Morris, S Mandava… - US Patent …, 2016 - Google Patents
Examples are disclosed for probabilistic dynamic random access memory (DRAM) row
repair. In some examples, using a row hammer limit for DRAM and a maximum activation …
repair. In some examples, using a row hammer limit for DRAM and a maximum activation …
Techniques for determining victim row addresses in a volatile memory
S Mandava, BS Morris, S Sah, RM Stevens… - US Patent …, 2016 - Google Patents
BACKGROUND AS dynamic random access memory (DRAM) technolo gies are scaled to
Smaller dimensions, reliability issues arise that require mitigation by careful design. One …
Smaller dimensions, reliability issues arise that require mitigation by careful design. One …
Apparatus having dice to perorm refresh operations
T Shido - US Patent 9,570,142, 2017 - Google Patents
BACKGROUND Some semiconductor devices, such as a DRAM (Dynamic Random Access
Memory), perform a refresh operation to restore charge in memory cells to maintain the …
Memory), perform a refresh operation to restore charge in memory cells to maintain the …
Self repair device and method thereof
YB Shim - US Patent 9,508,456, 2016 - Google Patents
Various embodiments are directed to a self repair device and method which is capable of
selectively applying a row self repair mode and a column self repair mode during a package …
selectively applying a row self repair mode and a column self repair mode during a package …
Semiconductor memory devices and methods of operating the same
Y Ryu, CHA Sang-Uhn, H Chung, SJ Cho - US Patent 9,953,725, 2018 - Google Patents
A method of operating a semiconductor memory device is provided. In a method of operating
a semiconductor memory device including a memory cell array which includes a plurality of …
a semiconductor memory device including a memory cell array which includes a plurality of …
Memory device
HR Choi, SS Chi, HS Won - US Patent 10,497,421, 2019 - Google Patents
A memory device includes a plurality of memory cells, a weak address storage block
suitable for storing a weak address of a weak cell of which data retention time is shorter than …
suitable for storing a weak address of a weak cell of which data retention time is shorter than …
Device and method for repairing memory cell and memory system including the device
Provided are a method and an apparatus for repairing a memory cell in a memory test
system. A test device detects a fail address by testing a memory device according to a test …
system. A test device detects a fail address by testing a memory device according to a test …
Device and method for repairing memory cell and memory system including the device
Provided are a method and an apparatus for repairing a memory cell in a memory test
system. A test device detects a fail address by testing a memory device according to a test …
system. A test device detects a fail address by testing a memory device according to a test …
Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands
D Reed, A Gupta - US Patent 10,049,006, 2018 - Google Patents
A method for updating a DRAM memory array is disclosed. The method comprises: a)
transitioning the DRAM memory array from an idle state to a refresh state in accordance with …
transitioning the DRAM memory array from an idle state to a refresh state in accordance with …
Semiconductor device having error correction code (ECC) circuit
T Suzuki - US Patent 9,690,653, 2017 - Google Patents
An apparatus may comprise an ECC circuit configured to receive read data from a memory
cell array to correct, an error bit contained in a data portion of the read data responsive, at …
cell array to correct, an error bit contained in a data portion of the read data responsive, at …