Design and analysis of SRAM cell using body bias controller for low power applications
Low power consumption of electronic devices has become one of the most desirable factors
in the present day's technology. Static random access memory (SRAM) being an integral …
in the present day's technology. Static random access memory (SRAM) being an integral …
BPath-RO: A Performance-and Area-Efficient In Situ Delay Measurement Scheme for Digital IC
D Li, H Liang, H Zhang, Y Wang, M Yi, Y Lu, Z Huang - Electronics, 2023 - mdpi.com
Circuit delays are increasingly sensitive to process, voltage, temperature, and aging (PVTA)
variations, severely impacting circuit performance. Accurate measurement of circuit delay is …
variations, severely impacting circuit performance. Accurate measurement of circuit delay is …
A DLL-based body bias generator for minimum energy operation with independent P-well and N-well bias
This paper proposes an area-and energy-efficient DLL-based body bias generator (BBG) for
minimum energy operation that controls p-well and n-well bias independently so that the …
minimum energy operation that controls p-well and n-well bias independently so that the …
Surmounting Challenges in the Design of Low Power Real Time Clock IP for Advanced FinFET Technology Nodes
K Sukumar, S Vodnala, R Ayyagari… - … Conference on VLSI …, 2023 - ieeexplore.ieee.org
The Real Time Clock (RTC) IP is used in almost all electronic systems to maintain
computer's time. RTC IP has a very tight specification on the current consumption in the …
computer's time. RTC IP has a very tight specification on the current consumption in the …
Energy-harvesting applications and efficient power processing
T Hehn, A Bleitner, J Goeppert, D Hoffmann… - … 2030: On-Chip AI for an …, 2020 - Springer
In comparison to the original chapter in CHIPS 2020 vol. 2—New Vistas in Nanoelectronics
(Chap. 19: Hehn et al.,“Energy Harvesting Applications and Efficient Power Processing”, pp …
(Chap. 19: Hehn et al.,“Energy Harvesting Applications and Efficient Power Processing”, pp …
A Preliminary evaluation of building block computing systems
A building block computing system with inductive coupling Through Chip Interface (TCI)
consists of 3-D chip stack, each of which is small dedicated chips. By changing the …
consists of 3-D chip stack, each of which is small dedicated chips. By changing the …
Body bias optimization for real-time systems
The energy of real-time systems for embedded usage needs to be efficient without affecting
the system's ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising …
the system's ability to meet task deadlines. Dynamic body bias (BB) scaling is a promising …
A dynamic power reduction methodology based on reducing output transition rate
M Mostafa, AM Zaki, MW El-Kharashi… - 2019 IEEE Pacific …, 2019 - ieeexplore.ieee.org
Power consumption is one of the main challenges nowadays. Dynamic power is a
challenging source of power dissipation for dynamic logic. Dynamic power is affected by …
challenging source of power dissipation for dynamic logic. Dynamic power is affected by …
[PDF][PDF] The Complete Switching Circuit Design for CPU Joint Body Biasing and Supply Voltage Scaling
DR SULAIMAN, II HAMARASH… - ZANCO Journal of …, 2019 - conferences.su.edu.krd
The modern CPU technology scaling with increasing transistor density causes an
exponential growth of both dynamic and static power dissipations that affecting the …
exponential growth of both dynamic and static power dissipations that affecting the …
[PDF][PDF] A Real Chip Evaluation of a CNN Accelerator SNACC
SNACC (Scalable Neuro Accelerator Core with Cubic integration) is an accelerator for deep
neural network, which can improve the performance by increasing the number of stacked …
neural network, which can improve the performance by increasing the number of stacked …