Modern electronics depend on nanoscaled technologies that present new challenges in
terms of testing and diagnostics. Memories are particularly prone to defects since they …

The class of dynamic faults has been recently shown to be an important class of faults for the
new technologies of Random Access Memories (RAM) with significant impact on defect-per …

Manufacturing defects can cause hard-to-detect (HTD) faults in fin field-effect transistor
(FinFET) static random access memories (SRAMs). Detection of these faults, such as …

In this paper, all linked and unlinked static and two-operation dynamic faults are considered.
A classification for their description is introduced. To generate a test algorithm for detection …

This paper introduces a novel solution for building fault aware memory built-in self-test
infrastructure based on rules of fault periodicity and regularity in memories and test …

Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an
important challenge for manufacturing testing in scaled technologies, as they may lead to …

Dynamic faults detection is important in recent Random Access Memory (RAM)
technologies. However, there is less research performed to design memory test algorithms …

The miniaturization of CMOS technology is likely to reach its limit due to short-channel
effects. New transistor technologies, including FinFET technology, were developed to deal …

Memory testing commonly faces two issues: the characterization of detailed and realistic
fault models, and the definition of time-efficient test algorithms to detect them. March tests …

Recent advances in access-transistor-free memristive crossbars have demonstrated the
potential of memristor arrays as high-density and ultra-low-power memory. However, with …