An investigation of PLL synchronization techniques for distributed generation sources in the grid-connected mode of operation
SV Kulkarni, DN Gaonkar - Electric Power Systems Research, 2023 - Elsevier
In recent years, the proliferation of grid-connected microgrid systems has witnessed a
remarkable surge, driven by the need to enhance the availability and reliability of renewable …
remarkable surge, driven by the need to enhance the availability and reliability of renewable …
Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application
M Sivasakthi, P Radhika - AEU-International Journal of Electronics and …, 2024 - Elsevier
This article introduces a novel approach of hybrid current-starved ring voltage-controlled
oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high …
oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high …
Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application
The phase frequency detector/charge pump is a significant source to raise the in-band
phase noise of the phase-locked loop (PLL). The proposed CMOS-based pass transistor …
phase noise of the phase-locked loop (PLL). The proposed CMOS-based pass transistor …
Design & Implementation of High Speed and Low Power PLL Using GPDK 45 nm Technology
NA Badiger, S Iyer - Journal of The Institution of Engineers (India): Series B, 2024 - Springer
With progress in the design of phase locked loop (PLL) circuit, critical parameters like, power
dissipation, phase noise, and area, has had to be considered within the analysis. The key …
dissipation, phase noise, and area, has had to be considered within the analysis. The key …
Transmission gate based PFD free of glitches for fast locking PLL with reduced reference spur
R Singh, KKA Majeed, U Nanda - … 2021, Vellore, India, February 11-13 …, 2021 - Springer
This work has been paying attention to design and implement a Transmission gate phase
frequency detector (TG-PFD) for Fast locking and low Reference Spur PLL working in Giga …
frequency detector (TG-PFD) for Fast locking and low Reference Spur PLL working in Giga …
Design of Current Starved Voltage Controlled Oscillator with Phase Locked Loop to Estimate the Process Corner Analysis.
K Annamma, S Saxena… - Majlesi Journal of …, 2024 - search.ebscohost.com
This paper consists of a performance comparison of Current Starved Voltage Controlled
Oscillator (CSVCO) for Phase Locked Loop (PLL). The design of Current Starved VCO is …
Oscillator (CSVCO) for Phase Locked Loop (PLL). The design of Current Starved VCO is …
Design and implementation of CSVCO for PLL applications
K Annamma - 2024 - researchsquare.com
This paper depicts the design and performance analysis of Current Starved Voltage
Controlled Oscillator (CSVCO), With different low leakage power techniques. This low power …
Controlled Oscillator (CSVCO), With different low leakage power techniques. This low power …